store_controller.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY store_controller IS 
           PORT (ready : IN  std_logic;
                 reset : IN  std_logic;
                 clk   : IN  std_logic;
                 read_write  : IN  std_logic;
		 we,oe       : OUT std_logic);
END store_controller;

ARCHITECTURE state_machine OF store_controller IS
     TYPE state_type IS array (2 DOWNTO 0) OF std_logic;
     CONSTANT idle     : state_type := "000";
     CONSTANT decision : state_type := "001";
     CONSTANT read     : state_type := "100";
     CONSTANT write    : state_type := "010";
     SIGNAL   state    : state_type;
BEGIN
     state_transfer:PROCESS (clk)
     BEGIN
          IF (reset ='1') THEN
              state <= idle;
          ELSIF (clk'event AND clk ='1') THEN
             CASE state IS
                  WHEN idle => IF (ready ='1') THEN
                                   state <= decision;
                               ELSE
                                   state <= idle;
                               END IF;
                  WHEN decision => IF (read_write ='1') THEN
                                       state <= read;
                                   ELSE
                                       state <= write;
                                   END IF;
                  WHEN read => IF (ready ='1') THEN
                                   state <= idle;
                               ELSE
                                   state <= read;
                               END IF;
                  WHEN write => IF (ready ='1') THEN
                                    state <= idle;
                                ELSE
                                    state <= write;
                                END IF;
                  WHEN OTHERS => STATE <= "---";
             END CASE;
          END IF;
     END PROCESS;
     oe <= state(2);
     we <= state(1);
END state_machine;