sync_rsdff.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY sync_rsdff IS 
           PORT (d,clk : IN  std_logic;
                 set   : IN  std_logic;
                 reset : IN  std_logic;
		 q,qb  : OUT std_logic);
END sync_rsdff;

ARCHITECTURE rtl_arc OF sync_rsdff IS
BEGIN
	 PROCESS (clk)
         BEGIN
              IF (clk'event AND clk ='1') THEN
                  IF (set ='0' AND reset ='1') THEN
                      q  <= '1';
                      qb <= '0';
                  ELSIF (set ='1' AND reset ='0') THEN
                      q  <= '0';
                      qb <= '1';
                  ELSE
                      q  <= d;
                      qb <= NOT d;
                  END IF;
              END IF;
         END PROCESS;
END rtl_arc;