async_rdff.vhd

来自「数字逻辑基础与Verilog设计,针对verilog语言的特点」· VHDL 代码 · 共 24 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY async_rdff IS 
           PORT (d,clk  : IN  std_logic;
                 reset  : IN  std_logic;
		 q,qb   : OUT std_logic);
END async_rdff;

ARCHITECTURE rtl_arc OF async_rdff IS
BEGIN
	 PROCESS (clk,reset)
         BEGIN
              IF (reset ='0') THEN
                  q  <= '0';
                  qb <= '1';
              ELSIF (clk'event AND clk ='1') THEN
                  q  <= d;
                  qb <= NOT d;
              END IF;
         END PROCESS;
END rtl_arc;