reg_74ls374.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY reg_74LS374 IS 
           PORT (d   : IN  std_logic_vector(7 DOWNTO 0);
                 oe  : IN  std_logic;
                 clk : IN  std_logic;
		 q   : INOUT std_logic_vector(7 DOWNTO 0));
END reg_74LS374;

ARCHITECTURE rtl_arc OF reg_74LS374 IS
BEGIN
	 PROCESS (clk,oe)
         BEGIN
              IF (oe ='0') THEN
                  IF (clk'event AND clk ='1') THEN 
                      q <= d;
                  ElSE
                      q <= q;
                  END IF;
              ELSE
                  q <= "ZZZZZZZZ";
              END IF;
         END PROCESS;
END rtl_arc;