async_counter.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY async_rdff IS 
           PORT (d,clk  : IN  std_logic;
                 reset  : IN  std_logic;
		 q,qb   : OUT std_logic);
END async_rdff;

ARCHITECTURE rtl_arc OF async_rdff IS
BEGIN
	 PROCESS (clk,reset)
         BEGIN
              IF (reset ='0') THEN
                  q  <= '0';
                  qb <= '1';
              ELSIF (clk'event AND clk ='1') THEN
                  q  <= d;
                  qb <= NOT d;
              END IF;
         END PROCESS;
END rtl_arc;

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY async_counter IS 
           PORT (clk   : IN  std_logic;
                 reset : IN  std_logic;
		 q     : OUT std_logic_vector(3 DOWNTO 0));
END async_counter;

ARCHITECTURE rtl_arc OF async_counter IS
     COMPONENT async_rdff
            PORT (d,clk  : IN  std_logic;
                  reset  : IN  std_logic;
		  q,qb   : OUT std_logic);
     END COMPONENT;
     SIGNAl  q_tmp : std_logic_vector(4 DOWNTO 0);
BEGIN
     q_tmp(0) <= clk;
     G1:FOR i IN 0 TO 3 GENERATE
        async_rdffx: async_rdff
                  PORT MAP (clk   => q_tmp(i),
                            reset => reset,
                            d     => q_tmp(i+1),
                            q     => q(i),
                            qb    => q_tmp(i+1));
     END GENERATE G1;
END rtl_arc;