countern.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_unsigned.ALL;

ENTITY counterN IS 
           GENERIC (n : integer:=8);
           PORT (clk    : IN  std_logic;
                 areset : IN  std_logic;
                 sset   : IN  std_logic;
                 enable : IN  std_logic;
                 updown : IN  std_logic;
		 q      : BUFFER std_logic_vector(n-1 DOWNTO 0));
END counterN;

ARCHITECTURE rtl_arc OF counterN IS
BEGIN
     PROCESS (clk,areset)
     BEGIN
          IF (areset ='1') THEN
              q <= (OTHERS => '0');
          ELSIF (clk'event AND clk ='1') THEN
              IF (sset ='1') THEN
                  q <= (OTHERS => '1');
              ELSIF (enable ='1') THEN
                  IF (updown ='1') THEN 
                      q <= q +1;
                  ELSE
                      q <= q -1;
                  END IF;
              ELSE
                  q <= q;
              END IF;
          END IF;
     END PROCESS;
END rtl_arc;