shift_regn.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_unsigned.ALL;

PACKAGE example IS
        PROCEDURE shift (din,s : IN  std_logic_vector;
                         SIGNAL dout : OUT std_logic_vector);
END example;

PACKAGE BODY example IS
           PROCEDURE shift (din,s : IN  std_logic_vector;
                            SIGNAL dout : OUT std_logic_vector) IS
           VARIABLE s_temp : integer;
           BEGIN
                s_temp := conv_integer(s);
                FOR i IN din'RANGE LOOP
                    IF (s_temp+i <= din'left) THEN
                        dout(s_temp+i) <= din(i);
                    ELSE
                        dout(s_temp+i-1- din'left) <= din(i);
                    END IF;
                END LOOP;
           END shift;
END example;

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
--USE WORK.exmple.ALL;

ENTITY shift_regN IS 
           GENERIC (n : integer :=3);
           PORT (din  : IN  std_logic_vector((2**n-1) DOWNTO 0);
                 s    : IN  std_logic_vector(n-1 DOWNTO 0);
                 en   : IN  std_logic;
                 clk  : IN  std_logic;
		 dout : OUT std_logic_vector((2**n-1) DOWNTO 0));
END shift_regN;

ARCHITECTURE structure_arc OF shift_regN IS
BEGIN
     PROCESS (clk)
     BEGIN
          IF (clk'event AND clk ='1') THEN
              IF (en ='0') THEN
                  dout <= din;
              ELSE
                  shift(din,s,dout);
              END IF;
          END IF;
     END PROCESS;
END structure_arc;