tff.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY tff IS 
           PORT (t,clk  : IN  std_logic;
		 q,qb   : OUT std_logic);
END tff;

ARCHITECTURE rtl_arc OF tff IS
     SIGNAL q_temp,qb_temp : std_logic;
BEGIN
	 PROCESS(clk)
         BEGIN
              IF (clk'event AND clk ='1') THEN
                  IF (t ='1') THEN
                      q_temp  <= NOT q_temp;
                      qb_temp <= NOT qb_temp;
                  ELSE
                      q_temp  <= q_temp;
                      qb_temp <= qb_temp;
                  END IF;
              END IF;
              q  <= q_temp;
              qb <= qb_temp;
         END PROCESS;
END rtl_arc;