bus_and.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY bus_and IS 
           PORT (data_bus	: IN  std_logic_vector(7 DOWNTO 0);
                 q  	: OUT  std_logic);
END bus_and;

ARCHITECTURE rtl OF bus_and IS
         SIGNAL  tmp : std_logic;
BEGIN
         P1: PROCESS(data_bus)
         BEGIN
              tmp <= '1';
              FOR i IN 7 DOWNTO 0 LOOP
                  tmp <= data_bus(i) AND tmp;
              END LOOP;
              q <= tmp;
         END PROCESS P1;
END rtl;