reset_dff1.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY reset_dff1 IS 
           PORT (clk,reset  : IN  std_logic;
                 d  : IN  std_logic;
                 q  : OUT std_logic);
END reset_dff1;

ARCHITECTURE rtl OF reset_dff1 IS
BEGIN
     PROCESS
     BEGIN
          IF (reset = '1') THEN 
              q <= '0';
          ELSIF (clk'event AND clk = '1') THEN
              q <= d;
          END IF;
          WAIT ON clk,reset;
     END PROCESS;
END rtl;