logic_and.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY logic_and IS
           PORT (a : IN  std_logic_vector(7 DOWNTO 0);
                 b : IN  std_logic_vector(7 DOWNTO 0);
                 mask : IN  std_logic_vector(7 DOWNTO 0);
                 q : OUT std_logic_vector(7 DOWNTO 0));
END logic_and;

ARCHITECTURE rtl OF logic_and IS
BEGIN
     PROCESS(a,b,mask)
     BEGIN
          FOR i IN 7 DOWNTO 0 LOOP
              IF (mask(i)= '1') THEN
                  NEXT;
              ELSE 
                  q(i) <= a(i) AND b(i);
              END IF;
          END LOOP;
     END PROCESS;
END rtl;