rsff.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY rsff IS
           PORT (s,r  : IN  std_logic;
                 q,qb : OUT std_logic);
END rsff;

ARCHITECTURE rtl OF rsff IS
BEGIN
         PROCESS (s,r)
         VARIABLE  last_state : std_logic;
         BEGIN
              ASSERT (NOT(s = '1' AND r = '1'))
              REPORT "Both s and r equal to '1'."
              SEVERITY error;
              IF (s = '0' AND r = '0') THEN
                  last_state := last_state;
              ELSIF (s = '0' AND r = '1') THEN
                  last_state := '0';
              ELSE
                  last_state := '1';
              END IF;
              q <= last_state;
              qb <= NOT(last_state);
         END PROCESS;
END rtl;