subadd.vhd.bak

一个四位二进制加/减运算器。 要求：当控制端G＝0时做加运算

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY subadd IS
PORT(A:IN STD_LOGIC_VECTOR (3 DOWNTO 0);
B:IN STD_LOGIC_VECTOR (3 DOWNTO 0);
G:IN STD_LOGIC;
Co :OUT STD_LOGIC;
S:OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END subadd;
ARCHITECTURE RTL OF subadd IS

SIGNAL y:STD_LOGIC_VECTOR (3 DOWNTO 0);
BEGIN
PROCESS(A,B,G,y)
BEGIN
IF(G='0')THEN
y<=A+B;
ELSE IF(A>B)THEN
y<=A-B;
ELSE
y<=B-A;
END IF;
IF(G='1' AND A<B)THEN
Co<='1';
ELSE
Co<='0';
END IF;
S<=y;
END PROCESS;
END RTL;