subadd.qsf

一个四位二进制加/减运算器。 要求：当控制端G＝0时做加运算

# Copyright (C) 1991-2008 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		subadd_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY Cyclone
set_global_assignment -name DEVICE EP1C6Q240C8
set_global_assignment -name TOP_LEVEL_ENTITY subadd
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:39:21  APRIL 28, 2009"
set_global_assignment -name LAST_QUARTUS_VERSION 8.1
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name VHDL_FILE subadd.vhd
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name SIMULATION_MODE TIMING
set_global_assignment -name VECTOR_WAVEFORM_FILE subadd.vwf
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE subadd.vwf
set_location_assignment PIN_223 -to G
set_location_assignment PIN_236 -to A[0]
set_location_assignment PIN_235 -to A[1]
set_location_assignment PIN_234 -to A[2]
set_location_assignment PIN_233 -to A[3]
set_location_assignment PIN_240 -to B[0]
set_location_assignment PIN_239 -to B[1]
set_location_assignment PIN_238 -to B[2]
set_location_assignment PIN_237 -to B[3]
set_location_assignment PIN_6 -to Co
set_location_assignment PIN_1 -to S[0]
set_location_assignment PIN_2 -to S[1]
set_location_assignment PIN_3 -to S[2]
set_location_assignment PIN_4 -to S[3]