subadd.fit.rpt

一个四位二进制加/减运算器。 要求：当控制端G＝0时做加运算

Fitter report for subadd
Tue Apr 28 17:26:42 2009
Quartus II Version 8.1 Build 163 10/28/2008 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Incremental Compilation Preservation Summary
  5. Incremental Compilation Partition Settings
  6. Incremental Compilation Placement Preservation
  7. Pin-Out File
  8. Fitter Resource Usage Summary
  9. Input Pins
 10. Output Pins
 11. I/O Bank Usage
 12. All Package Pins
 13. Output Pin Default Load For Reported TCO
 14. Fitter Resource Utilization by Entity
 15. Delay Chain Summary
 16. Pad To Core Delay Chain Fanout
 17. Non-Global High Fan-Out Signals
 18. Interconnect Usage Summary
 19. LAB Logic Elements
 20. LAB Signals Sourced
 21. LAB Signals Sourced Out
 22. LAB Distinct Inputs
 23. Fitter Device Options
 24. Estimated Delay Added for Hold Timing
 25. Advanced Data - General
 26. Advanced Data - Placement Preparation
 27. Advanced Data - Placement
 28. Advanced Data - Routing
 29. Fitter Messages
 30. Fitter Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------+
; Fitter Summary                                                   ;
+-----------------------+------------------------------------------+
; Fitter Status         ; Successful - Tue Apr 28 17:26:42 2009    ;
; Quartus II Version    ; 8.1 Build 163 10/28/2008 SJ Full Version ;
; Revision Name         ; subadd                                   ;
; Top-level Entity Name ; subadd                                   ;
; Family                ; Cyclone                                  ;
; Device                ; EP1C6Q240C8                              ;
; Timing Models         ; Final                                    ;
; Total logic elements  ; 19 / 5,980 ( < 1 % )                     ;
; Total pins            ; 14 / 185 ( 8 % )                         ;
; Total virtual pins    ; 0                                        ;
; Total memory bits     ; 0 / 92,160 ( 0 % )                       ;
; Total PLLs            ; 0 / 2 ( 0 % )                            ;
+-----------------------+------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                      ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                             ; Setting                        ; Default Value                  ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                             ; EP1C6Q240C8                    ;                                ;
; Fit Attempts to Skip                                               ; 0                              ; 0.0                            ;
; Use smart compilation                                              ; Off                            ; Off                            ;
; Use TimeQuest Timing Analyzer                                      ; Off                            ; Off                            ;
; Router Timing Optimization Level                                   ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                                        ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                                           ; 1.0                            ; 1.0                            ;
; Optimize Hold Timing                                               ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Multi-Corner Timing                                       ; Off                            ; Off                            ;
; Optimize Timing                                                    ; Normal compilation             ; Normal compilation             ;
; Optimize Timing for ECOs                                           ; Off                            ; Off                            ;
; Regenerate full fit report during ECO compiles                     ; Off                            ; Off                            ;
; Optimize IOC Register Placement for Timing                         ; On                             ; On                             ;
; Limit to One Fitting Attempt                                       ; Off                            ; Off                            ;
; Final Placement Optimizations                                      ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                        ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                      ; 1                              ; 1                              ;
; Slow Slew Rate                                                     ; Off                            ; Off                            ;
; PCI I/O                                                            ; Off                            ; Off                            ;