regkeys

用verilog HDL编写的并串转换模块

CommandLine
D:\ISE10.1anzhuang\ISE\bin\nt\unwrapped\netgen.exe -ise E:/01. ISE9.1/apgy2/chuan2/chuan2.ise -intstyle ise -s 7 -pcf converter.pcf -sdf_anno true -sdf_path netgen/par -insert_glbl true -insert_pp_buffers false -w -dir netgen/par -ofmt verilog -sim converter.ncd converter_timesim.v
s
FormatString
netgen [-ecn <tool_name>] [-sim] [-sta] [-ofmt verilog] [-aka] [-bx <BRAM_output_dir>] {-bd <BRAM_data_file>[tag <tagName>]} [-dir <dir_name>] [-fn] [-gp <port_name>] [-intstyle ise|xflow|silent] [-ism] [-insert_glbl <true_or_false>] [-insert_pp_buffers <true_or_false>][-ne] [-ngm <ngm_file>] [-mhf] [-module] [-pcf <pcf_file>] [-pf] [-s <speed>][-sdf_anno <true_or_false>] [-sdf_path [<path>]] [-shm] [-tb] [-ti <top_instance_name>][-tm <top_module_name>] [-tp <port_name>] [-ul] [-vcd] [-w] [--10ps] [--cd] [--log <log_file>][--quiet] [--r] [--verbose] [--debug] [--cleanup] [--suh <true_or_false>] [--wraplog <log_file>] [--ub] <infile> [<outfile[.v]>]
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