regkeys

来自「用verilog HDL编写的并串转换模块」· 代码 · 共 7 行

CommandLine
D:/Xilinx/10.1/ISE/bin/nt/unwrapped/trce.exe -ise E:/01. ISE9.1/apgy2/chuan2/chuan2.ise -intstyle ise -v 3 -s 7 -xml converter converter.ncd -o converter.twr converter.pcf
s
FormatString
trce.exe ([-e|-v [<limit:0,2000000000>]] [-l <limit:0,2000000000>] [-n [<limit:0,2000000000>]] [-u [<limit:0,2000000000>]] [-skew] [-a] [--p] [-s <speed>] [-o <report[.twr]>] [--m] [-stamp <stampfile>] [-tsi <tsifile[.tsi]>] [-xml <report[.twx]>] [-nodatasheet] [-timegroups] [-fastpaths] [-intstyle ise|xflow|silent] [-ise <projectfile>] [--ucf <constraint[.ucf]>] <design[.ncd]> [<constraint[.pcf]>]) | ([-run <macro[.xtm]> [<design[.ncd]> [<constraint[.pcf]>]]] [-intstyle ise|xflow|silent] [-ise <projectfile>])
s