regkeys

来自「用verilog HDL编写的并串转换模块」· 代码 · 共 7 行

CommandLine
D:\Xilinx\10.1\ISE\bin\nt\unwrapped\xst.exe -ise E:/01. ISE9.1/apgy2/chuan2/chuan2.ise -intstyle ise -ifn E:/01. ISE9.1/apgy2/chuan2/converter.xst -ofn E:/01. ISE9.1/apgy2/chuan2/converter.syr -finalclean 1
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FormatString
xst [-ifn <InputFile>] [-ofn <OutputFile>] [-ise <iseProjectFile>] [--quiet] [-intstyle <Style>] [--deb <DebugLevel>] [--finalclean <Clean>] [--PcubeFlow] [--globOptFlow] [--XstNtrc]
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