counterpart3.v

an up down counter in verilog

module counterPart3(ck,ld,data,count_to,reset,     //semnale de intrare               
                    in1,in2,in3,in4,        
                    count,tercnt);                 //semnale de iesire

parameter width=4;

input               ck,ld,reset;
input [width-1:0]   data,count_to;
input               in1,in2,in3,in4;

output              tercnt;
output [width-1:0]  count;

wire [width-1:0] d;

mux21 mux21Part1(.in1(data[0]),
                 .in2(in1),
                 .sel(~ld),
                 .out(d[0])  
                 );

bistabil bistabilPart1(.d(d[0]),
                       .q(count[0]),
                       .reset(~reset),
                       .ck(ck) 
                       );

mux21 mux21Part2(.in1(data[1]),
                 .in2(in2),
                 .sel(~ld),
                 .out(d[1])  
                 );

bistabil bistabilPart2(.d(d[1]),
                       .q(count[1]),
                       .reset(~reset),
                       .ck(ck) 
                       );

mux21 mux21Part3(.in1(data[2]),
                 .in2(in3),
                 .sel(~ld),
                 .out(d[2])  
                 );

bistabil bistabilPart3(.d(d[2]),
                       .q(count[2]),
                       .reset(~reset),
                       .ck(ck) 
                       );


mux21 mux21Part4(.in1(data[3]),
                 .in2(in4),
                 .sel(~ld),
                 .out(d[3])  
                 );

bistabil bistabilPart4(.d(d[3]),
                       .q(count[3]),
                       .reset(~reset),
                       .ck(ck) 
                       );

//tercnt

wire o1,o2,o3,o4;
assign o1 = count[0] & count_to[0];
assign o2 = count[1] & count_to[1];
assign o3 = count[2] & count_to[2];
assign o4 = count[3] & count_to[3];
assign tercnt = o1 & o2 & o3 & o4;

endmodule