multiply.v

a verilog programmed multiply unit algorithm

//repeta de n ori
//  - daca LSB A = 1 atunci
//      - P <= P + B
//  - deplaseaza cu o pozitie dreapta A (MSB A = LSB P)
//  - deplaseaza cu o pozitie dreapta P (MSB P = 0)
//- P contine MSB produs, iar A contine LSB produs


module multiply(ck,reset,ld,a,b,   //semnale de intrare
                produs,tercnt);    //semanle de iesire

parameter width=8;      //lungimea operanzilor
parameter width1=16;     //lungimea produsului, dublul operanzilor

input  [width-1:0]  a,b;
input               ck,reset,ld;

output [width1-1:0] produs;
output              tercnt;

reg    [width1-1:0] produs;
reg                 tercnt;

//semnale intermediare
wire                ld_rez,load,cmp,add,shiftA,shiftP,dec;
reg  [width-1:0]    a_net,b_net,p_net;
reg  [2:0]          stare;
reg  [3:0]          iter;
wire                zero = (iter==0);

//starile automatului
assign ld_rez = (stare==0);
assign load   = (stare==1);
assign cmp    = (stare==2);
assign add    = (stare==3);
assign shiftA = (stare==4);
assign shiftP = (stare==5);
assign dec    = (stare==6);

//calea de date
always@(posedge ck or negedge reset)
begin
   if(~reset)begin a_net<='b0; 
                   b_net<='b0;
                   p_net<='b0;
                   produs<='b0;
                   tercnt<='bx;
                   stare<=0;
             end   
      else 
         begin 
           if(load)begin a_net<=a;
                         b_net<=b;
                         produs<='b0;
                   end  
           if(add)
                         p_net<=p_net+b_net;
           if(shiftA)
                  begin  a_net<={1'b0,a_net[width-1:1]};
                         a_net[width-1]<=p_net[0];
                  end  
           if(shiftP) 
                  begin  p_net<={1'b0,p_net[width-1:1]};
                         p_net[width-1]<=0; 
                  end
           if(ld_rez)
                  begin  tercnt<=1;
                         produs<={p_net,a_net};
                  end
              else tercnt<=0;
           if(~reset||load) iter<='d8;
              else
                  if(dec) iter<=iter-1;
         end 

//calea de control
  if(reset)
     case(stare)
       0:if(ld)stare<=1;
       1:stare<=6;
       2:if(a_net[0]==1)stare<=3;
                   else stare<=4;         
       3:stare<=4;
       4:stare<=5;
       5:stare<=6;
       6:if(zero)stare<=0;
            else stare<=2; 
       default: stare<=0;
     endcase

end

endmodule