multiply.srr

a verilog programmed multiply unit algorithm

$ Start of Compile
#Tue Jun 05 18:41:48 2007

Synplify Verilog Compiler, version 5.1.2, built Apr 14 1999
Copyright (C) 1994-1999, Synplicity Inc.  All Rights Reserved

@I::"g:\my work\hdl lab\tema2\multiply.v"
Verilog syntax check successful!

Compiler output is up to date.  No re-compile necessary

Selecting top level module multiply
Synthesizing module multiply
@W:"g:\my work\hdl lab\tema2\multiply.v":41:22:41:34|Edge and condition mismatch
@W:"g:\my work\hdl lab\tema2\multiply.v":41:0:41:5|Feedback mux created for signal iter[3:0]. Did you forget the set/reset assignment for this signal?
@END
Process took 0.016 seconds realtime, 0.016 seconds cputime
Synplify Actel Technology Mapper, version 5.1.2, built Apr 14 1999
Copyright (C) 1994-1999, Synplicity Inc.  All Rights Reserved
Setting fanout limit to 16
@N:"g:\my work\hdl lab\tema2\multiply.v":41:0:41:5|Found counter in view:work.multiply(verilog) inst iter[3:0]
Automatic dissolve during optimization of view:work.multiply(verilog) of fadd2t_7t6(fadd2t)
Automatic dissolve during optimization of view:work.multiply(verilog) of fadd6_nc_5t0(fadd6_nc)
reset_y reset loading is 44
Replicating N_263, fanout 29, segments 2

Added 0 Buffers
Added 1 Cells via replication
Synthesized design as a chip
---------------------------------------
Resource Usage Report 

Target Part: a3265dx-s
Combinational Cells: 38
Sequential Cells:    48 of 510 (9%)
Total Cells:         86 of 985 (9%)
Clock Buffers:       2
IO Cells:            36

Details:
   and2:           2	comb:1
   and2b:          1	comb:1
   cm8:            15	comb:1
   cs2:            1	comb:1
   cy2a:           3	comb:1
   gand2:          1	comb:1
   maj3:           1	comb:1
   or2:            1	comb:1
   xnor2:          6	comb:1
   xor2:           7	comb:1

   dfm7a:          48	seq:1

   clkbuf:         2	clock buffer
   inbuf:          17	
   outbuf:         17	


		 ##### START TIMING REPORT #####
Set the Environment Variable SYNPLIFY_TIMING_REPORT_OLD to get the old timing report 


		 Performance Summary 
		*********************

          Requested     Estimated     Requested     Estimated          
Clock     Frequency     Frequency     Period        Period        Slack
-----------------------------------------------------------------------
ck        1.0 MHz       26.7 MHz      1000.0        37.4          962.6
=======================================================================


		 Interface Information 
		***********************

Input Ports: 

Port      Reference     User           Arrival     Required          
Name      Clock         Constraint     Time        Time         Slack
---------------------------------------------------------------------
a[0]      ck            0.0            0.0         992.6        992.6
a[1]      ck            0.0            0.0         992.6        992.6
a[2]      ck            0.0            0.0         992.6        992.6
a[3]      ck            0.0            0.0         992.6        992.6
a[4]      ck            0.0            0.0         992.6        992.6
a[5]      ck            0.0            0.0         992.6        992.6
a[6]      ck            0.0            0.0         992.6        992.6
a[7]      ck            0.0            0.0         992.6        992.6
b[0]      ck            0.0            0.0         992.6        992.6
b[1]      ck            0.0            0.0         992.6        992.6
b[2]      ck            0.0            0.0         992.6        992.6
b[3]      ck            0.0            0.0         992.6        992.6
b[4]      ck            0.0            0.0         992.6        992.6
b[5]      ck            0.0            0.0         992.6        992.6
b[6]      ck            0.0            0.0         992.6        992.6
b[7]      ck            0.0            0.0         992.6        992.6
ld        ck            0.0            0.0         992.6        992.6
reset     ck            0.0            0.0         976.0        976.0
=====================================================================


Output Ports: 

Port           Reference     User           Arrival     Required          
Name           Clock         Constraint     Time        Time         Slack
--------------------------------------------------------------------------
produs[0]      ck            0.0            10.6        1000.0       989.4
produs[1]      ck            0.0            10.6        1000.0       989.4
produs[2]      ck            0.0            10.6        1000.0       989.4
produs[3]      ck            0.0            10.6        1000.0       989.4
produs[4]      ck            0.0            10.6        1000.0       989.4
produs[5]      ck            0.0            10.6        1000.0       989.4
produs[6]      ck            0.0            10.6        1000.0       989.4
produs[7]      ck            0.0            10.6        1000.0       989.4
produs[8]      ck            0.0            10.6        1000.0       989.4
produs[9]      ck            0.0            10.6        1000.0       989.4
produs[10]     ck            0.0            10.6        1000.0       989.4
produs[11]     ck            0.0            10.6        1000.0       989.4
produs[12]     ck            0.0            10.6        1000.0       989.4
produs[13]     ck            0.0            10.6        1000.0       989.4
produs[14]     ck            0.0            10.6        1000.0       989.4
produs[15]     ck            0.0            10.6        1000.0       989.4
tercnt         ck            0.0            9.4         1000.0       990.6
==========================================================================


		Detailed Timing Report for  clock : ck 
		*******************************************
Requested Period 	  1000.0 ns
Estimated Period 	  37.4 ns
Worst Slack 	 	 962.6 ns

Start Points for Paths with Slack Worse than 967.5 ns : 

                                            Arrival          
Instance     Type      Pin     Net          Time        Slack
-------------------------------------------------------------
stare[0]     dfm7a     q       stare[0]     10.4        965.4
stare[1]     dfm7a     q       stare[1]     10.0        965.8
stare[2]     dfm7a     q       stare[2]     13.2        962.6
=============================================================


End Points for Paths with Slack Worse than 967.5 ns : 

                                         Required          
Instance     Type      Pin     Net       Time         Slack
-----------------------------------------------------------
iter[1]      dfm7a     s0      N_369     999.5        962.6
iter[2]      dfm7a     d2      N_369     999.5        962.6
===========================================================


A Critical Path with worst case slack = 962.6 ns:  

Instance/Net               Pin      Pin     Arrival     Delta     Fan
Name             Type      Name     Dir     Time        Delay     Out
---------------------------------------------------------------------
stare[2]         dfm7a     q        Out                 13.2         
stare[2]         Net                                              18 
G_216_1          cm8       d1       In      13.2                     
G_216_1          cm8       y        Out                 9.6          
N_263_1          Net                                              9  
G_217            cm8       d2       In      22.8                     
G_217            cm8       y        Out                 8.0          
N_273            Net                                              5  
G_170            cm8       s00      In      30.8                     
G_170            cm8       y        Out                 6.1          
N_369            Net                                              2  
iter[2]          dfm7a     d2       In      36.9                     
=====================================================================


		 ##### END TIMING REPORT #####

Mapper successful!
Process took 2.593 seconds realtime, 2.593 seconds cputime