prev_cmp_count10.tan.qmsg

来自「基于Quartus II的十进制加法计数器的项目设计」· QMSG 代码 · 共 10 行 · 第 1/5 页

{ "Info" "ITDB_FULL_TCO_RESULT" "CLK COUT CQI\[3\] 9.348 ns register " "Info: tco from clock \"CLK\" to destination pin \"COUT\" through register \"CQI\[3\]\" is 9.348 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.959 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 2.959 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_28 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 7; CLK Node = 'CLK'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "count10.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/count10/count10.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.779 ns) + CELL(0.711 ns) 2.959 ns CQI\[3\] 2 REG LC_X10_Y14_N7 12 " "Info: 2: + IC(0.779 ns) + CELL(0.711 ns) = 2.959 ns; Loc. = LC_X10_Y14_N7; Fanout = 12; REG Node = 'CQI\[3\]'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "1.490 ns" { CLK CQI[3] } "NODE_NAME" } } { "count10.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/count10/count10.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.67 % ) " "Info: Total cell delay = 2.180 ns ( 73.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.779 ns ( 26.33 % ) " "Info: Total interconnect delay = 0.779 ns ( 26.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "2.959 ns" { CLK CQI[3] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "2.959 ns" { CLK {} CLK~out0 {} CQI[3] {} } { 0.000ns 0.000ns 0.779ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "count10.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/count10/count10.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.165 ns + Longest register pin " "Info: + Longest register to pin delay is 6.165 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CQI\[3\] 1 REG LC_X10_Y14_N7 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y14_N7; Fanout = 12; REG Node = 'CQI\[3\]'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CQI[3] } "NODE_NAME" } } { "count10.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/count10/count10.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.573 ns) + CELL(0.590 ns) 1.163 ns altera_count10_COUT_signaltap_lcell 2 COMB LC_X10_Y14_N8 4 " "Info: 2: + IC(0.573 ns) + CELL(0.590 ns) = 1.163 ns; Loc. = LC_X10_Y14_N8; Fanout = 4; COMB Node = 'altera_count10_COUT_signaltap_lcell'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "1.163 ns" { CQI[3] altera_count10_COUT_signaltap_lcell } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.878 ns) + CELL(2.124 ns) 6.165 ns COUT 3 PIN PIN_1 0 " "Info: 3: + IC(2.878 ns) + CELL(2.124 ns) = 6.165 ns; Loc. = PIN_1; Fanout = 0; PIN Node = 'COUT'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "5.002 ns" { altera_count10_COUT_signaltap_lcell COUT } "NODE_NAME" } } { "count10.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/count10/count10.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.714 ns ( 44.02 % ) " "Info: Total cell delay = 2.714 ns ( 44.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.451 ns ( 55.98 % ) " "Info: Total interconnect delay = 3.451 ns ( 55.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "6.165 ns" { CQI[3] altera_count10_COUT_signaltap_lcell COUT } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "6.165 ns" { CQI[3] {} altera_count10_COUT_signaltap_lcell {} COUT {} } { 0.000ns 0.573ns 2.878ns } { 0.000ns 0.590ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "2.959 ns" { CLK CQI[3] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "2.959 ns" { CLK {} CLK~out0 {} CQI[3] {} } { 0.000ns 0.000ns 0.779ns } { 0.000ns 1.469ns 0.711ns } "" } } { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "6.165 ns" { CQI[3] altera_count10_COUT_signaltap_lcell COUT } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "6.165 ns" { CQI[3] {} altera_count10_COUT_signaltap_lcell {} COUT {} } { 0.000ns 0.573ns 2.878ns } { 0.000ns 0.590ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "CLK altera_count10_CLK_ae 3.567 ns Longest " "Info: Longest tpd from source pin \"CLK\" to destination pin \"altera_count10_CLK_ae\" is 3.567 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_28 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 7; CLK Node = 'CLK'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "count10.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/count10/count10.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.277 ns) + CELL(0.114 ns) 2.860 ns altera_count10_CLK_signaltap_lcell 2 COMB LC_X28_Y6_N2 1 " "Info: 2: + IC(1.277 ns) + CELL(0.114 ns) = 2.860 ns; Loc. = LC_X28_Y6_N2; Fanout = 1; COMB Node = 'altera_count10_CLK_signaltap_lcell'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "1.391 ns" { CLK altera_count10_CLK_signaltap_lcell } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.707 ns) + CELL(0.000 ns) 3.567 ns altera_count10_CLK_ae 3 PIN LC_X27_Y6_N0 0 " "Info: 3: + IC(0.707 ns) + CELL(0.000 ns) = 3.567 ns; Loc. = LC_X27_Y6_N0; Fanout = 0; PIN Node = 'altera_count10_CLK_ae'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "0.707 ns" { altera_count10_CLK_signaltap_lcell altera_count10_CLK_ae } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITD