prev_cmp_count10.tan.qmsg

来自「基于Quartus II的十进制加法计数器的项目设计」· QMSG 代码 · 共 10 行 · 第 1/5 页

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "auto_stp_external_clock_0 register sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|counter\[1\] register sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_buffer_write_address_sig\[5\] 150.08 MHz 6.663 ns Internal " "Info: Clock \"auto_stp_external_clock_0\" has Internal fmax of 150.08 MHz between source register \"sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|counter\[1\]\" and destination register \"sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_buffer_write_address_sig\[5\]\" (period= 6.663 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.422 ns + Longest register register " "Info: + Longest register to register delay is 6.422 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|counter\[1\] 1 REG LC_X23_Y12_N5 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X23_Y12_N5; Fanout = 5; REG Node = 'sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|counter\[1\]'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[1] } "NODE_NAME" } } { "../../libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "E:/Quartus 2/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 109 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.201 ns) + CELL(0.442 ns) 1.643 ns sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|Equal1~90 2 COMB LC_X24_Y12_N2 1 " "Info: 2: + IC(1.201 ns) + CELL(0.442 ns) = 1.643 ns; Loc. = LC_X24_Y12_N2; Fanout = 1; COMB Node = 'sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|Equal1~90'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "1.643 ns" { sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[1] sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~90 } "NODE_NAME" } } { "e:/quartus 2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/quartus 2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.441 ns) + CELL(0.590 ns) 2.674 ns sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|Equal1~94 3 COMB LC_X24_Y12_N5 9 " "Info: 3: + IC(0.441 ns) + CELL(0.590 ns) = 2.674 ns; Loc. = LC_X24_Y12_N5; Fanout = 9; COMB Node = 'sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|Equal1~94'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "1.031 ns" { sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~90 sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~94 } "NODE_NAME" } } { "e:/quartus 2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/quartus 2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.436 ns) + CELL(0.114 ns) 3.224 ns sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|segment_shift_var~47 4 COMB LC_X24_Y12_N8 15 " "Info: 4: + IC(0.436 ns) + CELL(0.114 ns) = 3.224 ns; Loc. = LC_X24_Y12_N8; Fanout = 15; COMB Node = 'sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|segment_shift_var~47'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "0.550 ns" { sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~94 sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|segment_shift_var~47 } "NODE_NAME" } } { "../../libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "E:/Quartus 2/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 109 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.229 ns) + CELL(0.442 ns) 4.895 ns sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count~93 5 COMB LC_X20_Y12_N1 2 " "Info: 5: + IC(1.229 ns) + CELL(0.442 ns) = 4.895 ns; Loc. = LC_X20_Y12_N1; Fanout = 2; COMB Node = 'sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count~93'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "1.671 ns" { sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|segment_shift_var~47 sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count~93 } "NODE_NAME" } } { "../../libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "E:/Quartus 2/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 97 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.218 ns) + CELL(0.309 ns) 6.422 ns sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_buffer_write_address_sig\[5\] 6 REG LC_X20_Y14_N8 1 " "Info: 6: + IC(1.218 ns) + CELL(0.309 ns) = 6.422 ns; Loc. = LC_X20_Y14_N8; Fanout = 1; REG Node = 'sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_buffer_write_address_sig\[5\]'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "1.527 ns" { sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count~93 sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[5] } "NODE_NAME" } } { "../../libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "E:/Quartus 2/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 109 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.897 ns ( 29.54 % ) " "Info: Total cell delay = 1.897 ns ( 29.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.525 ns ( 70.46 % ) " "Info: Total interconnect delay = 4.525 ns ( 70.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "6.422 ns" { sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[1] sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~90 sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~94 sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|segment_shift_var~47 sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count~93 sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[5] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "6.422 ns" { sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[1] {} sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~90 {} sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~94 {} sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|segment_shift_var~47 {} sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count~93 {} sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[5] {} } { 0.000ns 1.201ns 0.441ns 0.436ns 1.229ns 1.218ns } { 0.000ns 0.442ns 0.590ns 0.114ns 0.442ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.020 ns - Smallest " "Info: - Smallest clock skew is 0.020 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "auto_stp_external_clock_0 destination 2.962 ns + Shortest register " "Info: + Shortest clock path from clock \"auto_stp_external_clock_0\" to destination register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns auto_stp_external_clock_0 1 CLK PIN_29 197 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 197; CLK Node = 'auto_stp_external_clock_0'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "" { auto_stp_external_clock_0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_buffer_write_address_sig\[5\] 2 REG LC_X20_Y14_N8 1 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X20_Y14_N8; Fanout = 1; REG Node = 'sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_buffer_write_address_sig\[5\]'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "1.493 ns" { auto_stp_external_clock_0 sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[5] } "NODE_NAME" } } { "../../libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "E:/Quartus 2/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 109 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.60 % ) " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.40 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { auto_stp_external_clock_0 sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[5] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { auto_stp_external_clock_0 {} auto_stp_external_clock_0~out0 {} sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[5] {} } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "auto_stp_external_clock_0 source 2.942 ns - Longest register " "Info: - Longest clock path from clock \"auto_stp_external_clock_0\" to source register is 2.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns auto_stp_external_clock_0 1 CLK PIN_29 197 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 197; CLK Node = 'auto_stp_external_clock_0'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "" { auto_stp_external_clock_0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.711 ns) 2.942 ns sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|counter\[1\] 2 REG LC_X23_Y12_N5 5 " "Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X23_Y12_N5; Fanout = 5; REG Node = 'sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|counter\[1\]'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "1.473 ns" { auto_stp_external_clock_0 sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[1] } "NODE_NAME" } } { "../../libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "E:/Quartus 2/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 109 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.10 % ) " "Info: Total cell delay = 2.180 ns ( 74.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.762 ns ( 25.90 % ) " "Info: Total interconnect delay = 0.762 ns ( 25.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "2.942 ns" { auto_stp_external_clock_0 sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[1] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "2.942 ns" { auto_stp_external_clock_0 {} auto_stp_external_clock_0~out0 {} sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[1] {} } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { auto_stp_external_clock_0 sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[5] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { auto_stp_external_clock_0 {} auto_stp_external_clock_0~out0 {} sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[5] {} } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } } { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "2.942 ns" { auto_stp_external_clock_0 sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[1] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "2.942 ns" { auto_stp_external_clock_0 {} auto_stp_external_clock_0~out0 {} sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[1] {} } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "../../libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "E:/Quartus 2/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 109 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "../../libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "E:/Quartus 2/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 109 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "6.422 ns" { sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[1] sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~90 sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~94 sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|segment_shift_var~47 sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count~93 sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[5] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "6.422 ns" { sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[1] {} sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~90 {} sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~94 {} sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|segment_shift_var~47 {} sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count~93 {} sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[5] {} } { 0.000ns 1.201ns 0.441ns 0.436ns 1.229ns 1.218ns } { 0.000ns 0.442ns 0.590ns 0.114ns 0.442ns 0.309ns } "" } } { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { auto_stp_external_clock_0 sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[5] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { auto_stp_external_clock_0 {} auto_stp_external_clock_0~out0 {} sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[5] {} } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } } { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "2.942 ns" { auto_stp_external_clock_0 sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[1] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "2.942 ns" { auto_stp_external_clock_0 {} auto_stp_external_clock_0~out0 {} sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[1] {} } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "CQI\[0\] EN CLK 5.213 ns register " "Info: tsu for register \"CQI\[0\]\" (data pin = \"EN\", clock pin = \"CLK\") is 5.213 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.135 ns + Longest pin register " "Info: + Longest pin to register delay is 8.135 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns EN 1 PIN PIN_233 4 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_233; Fanout = 4; PIN Node = 'EN'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "" { EN } "NODE_NAME" } } { "count10.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/count10/count10.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.793 ns) + CELL(0.867 ns) 8.135 ns CQI\[0\] 2 REG LC_X10_Y14_N3 12 " "Info: 2: + IC(5.793 ns) + CELL(0.867 ns) = 8.135 ns; Loc. = LC_X10_Y14_N3; Fanout = 12; REG Node = 'CQI\[0\]'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "6.660 ns" { EN CQI[0] } "NODE_NAME" } } { "count10.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/count10/count10.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.342 ns ( 28.79 % ) " "Info: Total cell delay = 2.342 ns ( 28.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.793 ns ( 71.21 % ) " "Info: Total interconnect delay = 5.793 ns ( 71.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "8.135 ns" { EN CQI[0] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "8.135 ns" { EN {} EN~out0 {} CQI[0] {} } { 0.000ns 0.000ns 5.793ns } { 0.000ns 1.475ns 0.867ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "count10.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/count10/count10.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.959 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 2.959 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_28 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 7; CLK Node = 'CLK'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "count10.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/count10/count10.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.779 ns) + CELL(0.711 ns) 2.959 ns CQI\[0\] 2 REG LC_X10_Y14_N3 12 " "Info: 2: + IC(0.779 ns) + CELL(0.711 ns) = 2.959 ns; Loc. = LC_X10_Y14_N3; Fanout = 12; REG Node = 'CQI\[0\]'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "1.490 ns" { CLK CQI[0] } "NODE_NAME" } } { "count10.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/count10/count10.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.67 % ) " "Info: Total cell delay = 2.180 ns ( 73.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.779 ns ( 26.33 % ) " "Info: Total interconnect delay = 0.779 ns ( 26.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "2.959 ns" { CLK CQI[0] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "2.959 ns" { CLK {} CLK~out0 {} CQI[0] {} } { 0.000ns 0.000ns 0.779ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "8.135 ns" { EN CQI[0] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "8.135 ns" { EN {} EN~out0 {} CQI[0] {} } { 0.000ns 0.000ns 5.793ns } { 0.000ns 1.475ns 0.867ns } "" } } { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "2.959 ns" { CLK CQI[0] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "2.959 ns" { CLK {} CLK~out0 {} CQI[0] {} } { 0.000ns 0.000ns 0.779ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}