ascii.htm

利用XC9572－PQ44（Xilinx CPLD）制作的一款家用防盗报警器的Verilog源代码及原理图

FTCPE_alert_phone: FTCPE port map (alert_phone,alert_phone_T,NOT clk5hz,'0','0');
alert_phone_T <= ((EXP16_.EXP)
	OR (EXP17_.EXP)
	OR (alert_phone AND NOT state(1) AND state(3) AND state(0) AND 
	NOT state(2))
	OR (NOT sw1 AND alert_phone AND NOT state(1) AND NOT state(3) AND 
	NOT state(0) AND NOT state(2) AND NOT timer(0))
	OR (NOT sw1 AND alert_phone AND NOT state(1) AND NOT state(3) AND 
	NOT state(0) AND NOT state(2) AND timer(1))
	OR (NOT sw1 AND alert_phone AND NOT state(1) AND NOT state(3) AND 
	NOT state(0) AND NOT state(2) AND timer(2))
	OR (NOT sw1 AND alert_phone AND NOT state(1) AND NOT state(3) AND 
	NOT state(0) AND NOT state(2) AND timer(3)));

FTCPE_alert_sound: FTCPE port map (alert_sound,alert_sound_T,NOT clk5hz,'0','0');
alert_sound_T <= ((EXP23_.EXP)
	OR (EXP24_.EXP)
	OR (NOT sw1 AND alert_sound AND NOT state(1) AND NOT state(3) AND 
	NOT state(0) AND NOT state(2) AND NOT timer(0))
	OR (NOT sw1 AND alert_sound AND NOT state(1) AND NOT state(3) AND 
	NOT state(0) AND NOT state(2) AND timer(1))
	OR (NOT sw1 AND alert_sound AND NOT state(1) AND NOT state(3) AND 
	NOT state(0) AND NOT state(2) AND timer(2))
	OR (NOT sw1 AND alert_sound AND NOT state(1) AND NOT state(3) AND 
	NOT state(0) AND NOT state(2) AND timer(3))
	OR (NOT sw1 AND alert_sound AND NOT state(1) AND NOT state(3) AND 
	NOT state(0) AND NOT state(2) AND NOT timer(4)));

FDCPE_led1: FDCPE port map (led1,EXP10_.EXP,NOT clk5hz,'0','0');

FDCPE_power_ctrl: FDCPE port map (power_ctrl,power_ctrl_D,NOT clk5hz,'0','0');
power_ctrl_D <= ((EXP18_.EXP)
	OR (EXP19_.EXP)
	OR (sw1 AND NOT power_ctrl)
	OR (NOT power_ctrl AND state(1))
	OR (NOT power_ctrl AND state(3))
	OR (NOT power_ctrl AND state(0))
	OR (NOT power_ctrl AND state(2)));

FTCPE_ring_en: FTCPE port map (ring_en,ring_en_T,NOT clk5hz,'0','0');
ring_en_T <= ((EXP20_.EXP)
	OR (EXP21_.EXP)
	OR (NOT state(1) AND state(3) AND state(0) AND NOT state(2) AND 
	ring_en)
	OR (NOT sw1 AND NOT state(1) AND NOT state(3) AND NOT state(0) AND 
	NOT state(2) AND NOT timer(0) AND ring_en)
	OR (NOT sw1 AND NOT state(1) AND NOT state(3) AND NOT state(0) AND 
	NOT state(2) AND ring_en AND timer(1))
	OR (NOT sw1 AND NOT state(1) AND NOT state(3) AND NOT state(0) AND 
	NOT state(2) AND ring_en AND timer(2))
	OR (NOT sw1 AND NOT state(1) AND NOT state(3) AND NOT state(0) AND 
	NOT state(2) AND ring_en AND timer(3)));


ring_out_I <= ((clk5hz AND clk660hz)
	OR (NOT clk5hz AND clk540hz));
ring_out <= ring_out_I when ring_out_OE = '1' else 'Z';
ring_out_OE <= ring_en;

FTCPE_state0: FTCPE port map (state(0),state_T(0),NOT clk5hz,'0','0');
state_T(0) <= ((EXP26_.EXP)
	OR (EXP27_.EXP)
	OR (sw1 AND NOT state(1) AND NOT state(3) AND state(0) AND 
	NOT state(2))
	OR (NOT state(1) AND NOT state(3) AND NOT state(2) AND timer(0) AND 
	NOT timer(1) AND NOT timer(2) AND NOT timer(3) AND timer(4) AND timer(5) AND 
	timer(6) AND NOT timer(7))
	OR (NOT state(1) AND state(0) AND state(2) AND NOT timer(0) AND 
	timer(1) AND NOT timer(2) AND NOT timer(3) AND NOT timer(4) AND NOT timer(5) AND 
	NOT timer(6) AND NOT timer(7))
	OR (state(1) AND NOT state(3) AND state(0) AND NOT state(2) AND 
	timer(0) AND NOT timer(1) AND timer(2) AND timer(3) AND NOT timer(4) AND 
	NOT timer(5) AND NOT timer(6) AND NOT timer(7))
	OR (sw1 AND state(1) AND NOT state(3) AND NOT state(0) AND 
	NOT state(2) AND NOT timer(0) AND timer(1) AND timer(2) AND NOT timer(3) AND 
	NOT timer(4) AND NOT timer(5) AND NOT timer(6) AND NOT timer(7)));

FTCPE_state1: FTCPE port map (state(1),state_T(1),NOT clk5hz,'0','0');
state_T(1) <= ((EXP22_.EXP)
	OR (state(1) AND state(3) AND state(2))
	OR (sw1 AND NOT state(1) AND NOT state(3) AND NOT state(2))
	OR (NOT sw1 AND state(1) AND NOT state(3) AND NOT state(0) AND 
	NOT state(2))
	OR (state(1) AND state(3) AND state(0) AND timer(0) AND 
	NOT timer(1) AND NOT timer(2) AND NOT timer(3) AND NOT timer(4) AND NOT timer(5) AND 
	NOT timer(6) AND NOT timer(7))
	OR (state(1) AND state(3) AND NOT state(0) AND NOT timer(0) AND 
	timer(1) AND timer(2) AND timer(3) AND timer(4) AND timer(5) AND 
	timer(6) AND timer(7)));

FTCPE_state2: FTCPE port map (state(2),state_T(2),NOT clk5hz,'0','0');
state_T(2) <= ((EXP6_.EXP)
	OR (state(1) AND state(3) AND state(2)));

FDCPE_state3: FDCPE port map (state(3),state_D(3),NOT clk5hz,'0','0');
state_D(3) <= ((EXP28_.EXP)
	OR (NOT sw1 AND state(3) AND NOT state(2))
	OR (NOT state(1) AND state(3) AND NOT state(0))
	OR (state(3) AND state(0) AND NOT state(2))
	OR (state(3) AND NOT state(2) AND timer(1) AND timer(2) AND 
	timer(3) AND timer(4) AND timer(5) AND timer(6) AND timer(7))
	OR (sw1 AND state(1) AND NOT state(0) AND NOT state(2) AND 
	NOT timer(0) AND timer(1) AND timer(2) AND NOT timer(3) AND NOT timer(4) AND 
	NOT timer(5) AND NOT timer(6) AND NOT timer(7)));

FTCPE_timer0: FTCPE port map (timer(0),timer_T(0),NOT clk5hz,'0','0');
timer_T(0) <= ((EXP29_.EXP)
	OR (sw1 AND NOT state(1) AND NOT state(3) AND NOT state(2) AND 
	NOT timer(0))
	OR (sw1 AND state(1) AND state(3) AND NOT state(0) AND 
	NOT state(2) AND NOT timer(0) AND timer(4))
	OR (sw1 AND state(1) AND state(3) AND NOT state(0) AND 
	NOT state(2) AND NOT timer(0) AND timer(1) AND timer(3))
	OR (sw1 AND state(1) AND state(3) AND NOT state(0) AND 
	NOT state(2) AND NOT timer(0) AND NOT timer(1) AND NOT timer(3))
	OR (sw1 AND state(1) AND state(3) AND NOT state(0) AND 
	NOT state(2) AND NOT timer(0) AND timer(2) AND timer(3)));

FDCPE_timer1: FDCPE port map (timer(1),timer_D(1),NOT clk5hz,'0','0');
timer_D(1) <= ((timer(3).EXP)
	OR (EXP12_.EXP)
	OR (NOT state(1) AND NOT state(3) AND NOT state(2) AND NOT timer(1) AND 
	NOT timer(2) AND NOT timer(3) AND timer(4) AND timer(5) AND timer(6) AND 
	NOT timer(7))
	OR (NOT state(3) AND state(0) AND state(2) AND timer(1) AND 
	NOT timer(2) AND NOT timer(3) AND NOT timer(4) AND NOT timer(5) AND NOT timer(6) AND 
	NOT timer(7))
	OR (NOT state(3) AND NOT state(0) AND state(2) AND NOT timer(1) AND 
	NOT timer(2) AND NOT timer(3) AND NOT timer(4) AND NOT timer(5) AND NOT timer(6) AND 
	NOT timer(7))
	OR (state(1) AND state(3) AND NOT state(0) AND NOT state(2) AND 
	timer(1) AND timer(2) AND timer(3) AND timer(4) AND timer(5) AND 
	timer(6) AND timer(7))
	OR (state(1) AND NOT state(3) AND state(0) AND NOT state(2) AND 
	NOT timer(1) AND timer(2) AND timer(3) AND NOT timer(4) AND NOT timer(5) AND 
	NOT timer(6) AND NOT timer(7)));

FDCPE_timer2: FDCPE port map (timer(2),timer_D(2),NOT clk5hz,'0','0');
timer_D(2) <= ((EXP25_.EXP)
	OR (sw1 AND state(1) AND state(3) AND NOT state(0) AND 
	NOT state(2) AND timer(0))
	OR (sw1 AND state(1) AND state(3) AND NOT state(0) AND 
	NOT state(2) AND NOT timer(1))
	OR (sw1 AND state(1) AND state(3) AND NOT state(0) AND 
	NOT state(2) AND timer(4))
	OR (state(1) AND state(3) AND NOT state(0) AND NOT state(2) AND 
	timer(1) AND timer(2) AND timer(3) AND timer(4) AND timer(5) AND 
	timer(6) AND timer(7))
	OR (state(1) AND NOT state(3) AND state(0) AND NOT state(2) AND 
	timer(0) AND timer(2) AND timer(3) AND NOT timer(4) AND NOT timer(5) AND 
	NOT timer(6) AND NOT timer(7)));

FDCPE_timer3: FDCPE port map (timer(3),timer_D(3),NOT clk5hz,'0','0');
timer_D(3) <= ((EXP11_.EXP)
	OR (state(1) AND state(3) AND NOT state(0) AND NOT state(2) AND 
	timer(1) AND timer(2) AND timer(3) AND timer(4) AND timer(5) AND 
	timer(6) AND timer(7))
	OR (state(1) AND NOT state(3) AND state(0) AND NOT state(2) AND 
	timer(0) AND timer(2) AND timer(3) AND NOT timer(4) AND NOT timer(5) AND 
	NOT timer(6) AND NOT timer(7)));

FTCPE_timer4: FTCPE port map (timer(4),timer_T(4),NOT clk5hz,'0','0');
timer_T(4) <= ((EXP30_.EXP)
	OR (sw1 AND NOT state(1) AND NOT state(3) AND NOT state(2) AND 
	timer(4))
	OR (NOT sw1 AND timer(0) AND timer(1) AND timer(2) AND 
	timer(3))
	OR (state(1) AND timer(0) AND timer(1) AND timer(2) AND 
	timer(3))
	OR (state(3) AND timer(0) AND timer(1) AND timer(2) AND 
	timer(3))
	OR (state(2) AND timer(0) AND timer(1) AND timer(2) AND 
	timer(3)));

FTCPE_timer5: FTCPE port map (timer(5),timer_T(5),NOT clk5hz,'0','0');
timer_T(5) <= ((EXP15_.EXP)
	OR (state(2).EXP)
	OR (sw1 AND state(1) AND state(3) AND NOT state(0) AND 
	NOT state(2) AND timer(4) AND timer(5))
	OR (sw1 AND state(1) AND state(3) AND NOT state(0) AND 
	NOT state(2) AND timer(0) AND NOT timer(2) AND timer(5))
	OR (sw1 AND state(1) AND state(3) AND NOT state(0) AND 
	NOT state(2) AND NOT timer(1) AND timer(2) AND timer(5))
	OR (sw1 AND state(1) AND state(3) AND NOT state(0) AND 
	NOT state(2) AND NOT timer(1) AND NOT timer(3) AND timer(5))
	OR (sw1 AND state(1) AND state(3) AND NOT state(0) AND 
	NOT state(2) AND NOT timer(0) AND timer(2) AND timer(3) AND timer(5)));

FTCPE_timer6: FTCPE port map (timer(6),timer_T(6),NOT clk5hz,'0','0');
timer_T(6) <= ((EXP7_.EXP)
	OR (EXP8_.EXP)
	OR (sw1 AND state(1) AND state(3) AND NOT state(0) AND 
	NOT state(2) AND timer(0) AND NOT timer(2) AND timer(6))
	OR (sw1 AND state(1) AND state(3) AND NOT state(0) AND 
	NOT state(2) AND NOT timer(1) AND timer(2) AND timer(6))
	OR (sw1 AND state(1) AND state(3) AND NOT state(0) AND 
	NOT state(2) AND NOT timer(1) AND NOT timer(3) AND timer(6))
	OR (sw1 AND state(1) AND state(3) AND NOT state(0) AND 
	NOT state(2) AND NOT timer(3) AND timer(4) AND timer(6))
	OR (sw1 AND state(1) AND state(3) AND NOT state(0) AND 
	NOT state(2) AND NOT timer(0) AND timer(2) AND timer(3) AND timer(6)));

FTCPE_timer7: FTCPE port map (timer(7),timer_T(7),NOT clk5hz,'0','0');
timer_T(7) <= ((EXP13_.EXP)
	OR (EXP14_.EXP)
	OR (sw1 AND NOT state(1) AND NOT state(3) AND NOT state(2) AND 
	timer(7))
	OR (NOT sw1 AND timer(0) AND timer(1) AND timer(2) AND 
	timer(3) AND timer(4) AND timer(5) AND timer(6))
	OR (state(1) AND timer(0) AND timer(1) AND timer(2) AND 
	timer(3) AND timer(4) AND timer(5) AND timer(6))
	OR (state(3) AND timer(0) AND timer(1) AND timer(2) AND 
	timer(3) AND timer(4) AND timer(5) AND timer(6))
	OR (state(2) AND timer(0) AND timer(1) AND timer(2) AND 
	timer(3) AND timer(4) AND timer(5) AND timer(6)));

Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC9572XL-5-PC44


   --------------------------------  
  /6  5  4  3  2  1  44 43 42 41 40 \
 | 7                             39 | 
 | 8                             38 | 
 | 9                             37 | 
 | 10                            36 | 
 | 11        XC9572XL-5-PC44     35 | 
 | 12                            34 | 
 | 13                            33 | 
 | 14                            32 | 
 | 15                            31 | 
 | 16                            30 | 
 | 17                            29 | 
 \ 18 19 20 21 22 23 24 25 26 27 28 /
   --------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 KPR                              23 GND                           
  2 KPR                              24 KPR                           
  3 KPR                              25 KPR                           
  4 led1                             26 alert_sound                   
  5 clk5hz                           27 KPR                           
  6 KPR                              28 clk540hz                      
  7 KPR                              29 KPR                           
  8 KPR                              30 TDO                           
  9 KPR                              31 GND                           
 10 GND                              32 VCC                           
 11 KPR                              33 KPR                           
 12 KPR                              34 KPR                           
 13 KPR                              35 ring_out                      
 14 KPR                              36 KPR                           
 15 TDI                              37 KPR                           
 16 TMS                              38 KPR                           
 17 TCK                              39 KPR                           
 18 KPR                              40 alert_phone                   
 19 KPR                              41 VCC                           
 20 clk660hz                         42 power_ctrl                    
 21 VCC                              43 KPR                           
 22 sw1                              44 KPR                           


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         KPR  = Unused I/O with weak keeper (leave unconnected)
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc9572xl-5-PC44
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Power Mode                                  : STD
Ground on Unused IOs                        : OFF
Set I/O Pin Termination                     : KEEPER
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
Input Limit                                 : 54
Pterm Limit                                 : 25
</pre>
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