📄 main_ctrl.rpt
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cpldfit: version I.27 Xilinx Inc.
Fitter Report
Design Name: main_ctrl Date: 11-18-2008, 3:35PM
Device Used: XC9572XL-5-PC44
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
18 /72 ( 25%) 186 /360 ( 52%) 61 /216 ( 28%) 17 /72 ( 24%) 9 /34 ( 26%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 7/18 14/54 81/90 1/ 9
FB2 3/18 19/54 23/90 3/ 9
FB3 1/18 14/54 15/90 0/ 9
FB4 7/18 14/54 67/90 1/ 7
----- ----- ----- -----
18/72 61/216 186/360 5/34
* - Resource is exhausted
** Global Control Resources **
Signal 'clk5hz' mapped onto global clock net GCK1.
Global output enable net(s) unused.
Global set/reset net(s) unused.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 3 3 | I/O : 6 28
Output : 5 5 | GCK/IO : 1 3
Bidirectional : 0 0 | GTS/IO : 2 2
GCK : 1 1 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 9 9
** Power Data **
There are 18 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************* Summary of Mapped Logic ************************
** 5 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
led1 7 14 FB1_8 4 I/O O STD FAST RESET
ring_out 3 4 FB2_2 35 I/O O STD FAST
alert_phone 13 14 FB2_11 40 GTS/I/O O STD FAST RESET
power_ctrl 7 14 FB2_14 42 GTS/I/O O STD FAST SET
alert_sound 11 14 FB4_5 26 I/O O STD FAST RESET
** 13 Buried Nodes **
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
timer<6> 15 13 FB1_3 STD RESET
timer<3> 12 13 FB1_10 STD RESET
timer<1> 13 13 FB1_11 STD RESET
timer<7> 14 13 FB1_14 STD RESET
timer<5> 14 13 FB1_17 STD RESET
state<2> 6 12 FB1_18 STD RESET
ring_en 15 14 FB3_17 STD RESET
state<1> 10 13 FB4_2 STD RESET
timer<2> 10 13 FB4_8 STD RESET
state<0> 9 13 FB4_11 STD RESET
state<3> 9 13 FB4_13 STD RESET
timer<0> 9 13 FB4_15 STD RESET
timer<4> 9 13 FB4_18 STD RESET
** 4 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
clk5hz FB1_9 5 GCK/I/O GCK/I
clk660hz FB3_15 20 I/O I
sw1 FB3_17 22 I/O I
clk540hz FB4_11 28 I/O I
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X - Signal used as input to the macrocell logic.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 14/40
Number of signals used by logic mapping into function block: 14
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 /\5 0 FB1_1 (b) (b)
(unused) 0 0 \/5 0 FB1_2 1 I/O (b)
timer<6> 15 10<- 0 0 FB1_3 (b) (b)
(unused) 0 0 /\5 0 FB1_4 (b) (b)
(unused) 0 0 0 5 FB1_5 2 I/O
(unused) 0 0 \/2 3 FB1_6 3 I/O (b)
(unused) 0 0 \/5 0 FB1_7 (b) (b)
led1 7 7<- \/5 0 FB1_8 4 I/O O
(unused) 0 0 \/5 0 FB1_9 5 GCK/I/O GCK/I
timer<3> 12 10<- \/3 0 FB1_10 (b) (b)
timer<1> 13 8<- 0 0 FB1_11 6 GCK/I/O (b)
(unused) 0 0 /\5 0 FB1_12 (b) (b)
(unused) 0 0 \/4 1 FB1_13 (b) (b)
timer<7> 14 9<- 0 0 FB1_14 7 GCK/I/O (b)
(unused) 0 0 /\5 0 FB1_15 8 I/O (b)
(unused) 0 0 \/5 0 FB1_16 (b) (b)
timer<5> 14 9<- 0 0 FB1_17 9 I/O (b)
state<2> 6 5<- /\4 0 FB1_18 (b) (b)
Signals Used by Logic in Function Block
1: led1 6: sw1 11: timer<4>
2: state<0> 7: timer<0> 12: timer<5>
3: state<1> 8: timer<1> 13: timer<6>
4: state<2> 9: timer<2> 14: timer<7>
5: state<3> 10: timer<3>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
timer<6> .XXXXXXXXXXXXX.......................... 13
led1 XXXXXXXXXXXXXX.......................... 14
timer<3> .XXXXXXXXXXXXX.......................... 13
timer<1> .XXXXXXXXXXXXX.......................... 13
timer<7> .XXXXXXXXXXXXX.......................... 13
timer<5> .XXXXXXXXXXXXX.......................... 13
state<2> .XXXX.XXXXXXXX.......................... 12
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 19/35
Number of signals used by logic mapping into function block: 19
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB2_1 (b)
ring_out 3 0 0 2 FB2_2 35 I/O O
(unused) 0 0 0 5 FB2_3 (b)
(unused) 0 0 0 5 FB2_4 (b)
(unused) 0 0 0 5 FB2_5 36 I/O
(unused) 0 0 0 5 FB2_6 37 I/O
(unused) 0 0 0 5 FB2_7 (b)
(unused) 0 0 0 5 FB2_8 38 I/O
(unused) 0 0 0 5 FB2_9 39 GSR/I/O
(unused) 0 0 \/4 1 FB2_10 (b) (b)
alert_phone 13 8<- 0 0 FB2_11 40 GTS/I/O O
(unused) 0 0 /\4 1 FB2_12 (b) (b)
(unused) 0 0 \/1 4 FB2_13 (b) (b)
power_ctrl 7 2<- 0 0 FB2_14 42 GTS/I/O O
(unused) 0 0 /\1 4 FB2_15 43 I/O (b)
(unused) 0 0 0 5 FB2_16 (b)
(unused) 0 0 0 5 FB2_17 44 I/O
(unused) 0 0 0 5 FB2_18 (b)
Signals Used by Logic in Function Block
1: alert_phone 8: state<1> 14: timer<2>
2: clk540hz 9: state<2> 15: timer<3>
3: clk5hz 10: state<3> 16: timer<4>
4: clk660hz 11: sw1 17: timer<5>
5: power_ctrl 12: timer<0> 18: timer<6>
6: ring_en 13: timer<1> 19: timer<7>
7: state<0>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
ring_out .XXX.X.................................. 4
alert_phone X.....XXXXXXXXXXXXX..................... 14
power_ctrl ....X.XXXXXXXXXXXXX..................... 14
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 14/40
Number of signals used by logic mapping into function block: 14
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB3_1 (b)
(unused) 0 0 0 5 FB3_2 11 I/O
(unused) 0 0 0 5 FB3_3 (b)
(unused) 0 0 0 5 FB3_4 (b)
(unused) 0 0 0 5 FB3_5 12 I/O
(unused) 0 0 0 5 FB3_6 (b)
(unused) 0 0 0 5 FB3_7 (b)
(unused) 0 0 0 5 FB3_8 13 I/O
(unused) 0 0 0 5 FB3_9 14 I/O
(unused) 0 0 0 5 FB3_10 (b)
(unused) 0 0 0 5 FB3_11 18 I/O
(unused) 0 0 0 5 FB3_12 (b)
(unused) 0 0 0 5 FB3_13 (b)
(unused) 0 0 0 5 FB3_14 19 I/O
(unused) 0 0 0 5 FB3_15 20 I/O I
(unused) 0 0 \/5 0 FB3_16 24 I/O (b)
ring_en 15 10<- 0 0 FB3_17 22 I/O I
(unused) 0 0 /\5 0 FB3_18 (b) (b)
Signals Used by Logic in Function Block
1: ring_en 6: sw1 11: timer<4>
2: state<0> 7: timer<0> 12: timer<5>
3: state<1> 8: timer<1> 13: timer<6>
4: state<2> 9: timer<2> 14: timer<7>
5: state<3> 10: timer<3>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
ring_en XXXXXXXXXXXXXX.......................... 14
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 14/40
Number of signals used by logic mapping into function block: 14
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 \/5 0 FB4_1 (b) (b)
state<1> 10 5<- 0 0 FB4_2 25 I/O (b)
(unused) 0 0 0 5 FB4_3 (b)
(unused) 0 0 \/3 2 FB4_4 (b) (b)
alert_sound 11 6<- 0 0 FB4_5 26 I/O O
(unused) 0 0 /\3 2 FB4_6 (b) (b)
(unused) 0 0 \/5 0 FB4_7 (b) (b)
timer<2> 10 5<- 0 0 FB4_8 27 I/O (b)
(unused) 0 0 0 5 FB4_9 (b)
(unused) 0 0 \/3 2 FB4_10 (b) (b)
state<0> 9 4<- 0 0 FB4_11 28 I/O I
(unused) 0 0 /\1 4 FB4_12 (b) (b)
state<3> 9 4<- 0 0 FB4_13 (b) (b)
(unused) 0 0 /\4 1 FB4_14 29 I/O (b)
timer<0> 9 4<- 0 0 FB4_15 33 I/O (b)
(unused) 0 0 /\4 1 FB4_16 (b) (b)
(unused) 0 0 \/4 1 FB4_17 34 I/O (b)
timer<4> 9 4<- 0 0 FB4_18 (b) (b)
Signals Used by Logic in Function Block
1: alert_sound 6: sw1 11: timer<4>
2: state<0> 7: timer<0> 12: timer<5>
3: state<1> 8: timer<1> 13: timer<6>
4: state<2> 9: timer<2> 14: timer<7>
5: state<3> 10: timer<3>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
state<1> .XXXXXXXXXXXXX.......................... 13
alert_sound XXXXXXXXXXXXXX.......................... 14
timer<2> .XXXXXXXXXXXXX.......................... 13
state<0> .XXXXXXXXXXXXX.......................... 13
state<3> .XXXXXXXXXXXXX.......................... 13
timer<0> .XXXXXXXXXXXXX.......................... 13
timer<4> .XXXXXXXXXXXXX.......................... 13
0----+----1----+----2----+----3----+----4
0 0 0 0
******************************* Equations ********************************
********** Mapped Logic **********
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