zuihou.txt

用verilog HDL语言编写的家用空调温度控制器

module m(data,strt,up,down,stop,alert,y,in,clk,temp);
input  [7:0]  data;
input   [7:0] in;
input   clk,strt;
output   temp;
output    [7:0]  y;
output   up,down,stop,alert;
reg    up;
reg   stop;
reg     down;
reg    alert;
reg  temp;
reg  [7:0] y,  s;


always @ (posedge strt)
    
       if (temp)       temp=0;
       else             temp=1;
 
 always @ (posedge  clk)
   begin
  
   
       if (temp)
          begin 
            s=data;
            if(s[7:4]!=2) alert=1;
            else alert=0;
          end
       else s=8'h25;
    begin
      if(!alert)
         begin
              if (y[7:4]>s[7:4])
                  begin
                    down=1;
                    up=0;
                    stop=0;
                 
                      if (y[3:0]==0)
                           begin
                             y[7:4]=y[7:4]-1;
                             y[3:0]=9;
                           end
                   else y[3:0]= y[3:0]-1;
               end
              else  if (y[7:4]<s[7:4])
               begin  
                    up=1;
                    down=0;
                     stop=0;
                  if (y[3:0]==9)
                    begin 
                   y[3:0]=0;
                   y[7:4]=y[7:4]+1;
                     end
                  else  y[3:0]=y[3:0]+1;
                end
              else

                  begin
                     if (s[3:0]==y[3:0])
                       begin
                        stop=1;
                        up=0;
                      down=0;
                       end
                     else if (s[3:0]>y[3:0]) 
                          begin
                           up=1;
                          down=0;
                           stop=0;
                            y[3:0]=y[ 3:0]+1;
                           end
                     else  
                          begin
                             down=1;
                                 up=0;
                                stop=0;
                            y[3:0]=y[ 3:0]-1 ;
                            end
                     end
                
             end
        end
    end
endmodule