adder.map.qmsg

采用加法树流水线乘法构造八位乘法器

{ "Warning" "WSGN_SEARCH_FILE" "mult.vhd 2 1 " "Warning: Using design file mult.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mult-behave " "Info: Found design unit 1: mult-behave" {  } { { "mult.vhd" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/mult.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 mult " "Info: Found entity 1: mult" {  } { { "mult.vhd" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/mult.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult mult:inst2 " "Info: Elaborating entity \"mult\" for hierarchy \"mult:inst2\"" {  } { { "add.bdf" "inst2" { Schematic "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/add.bdf" { { 112 160 288 304 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "i mult.vhd(20) " "Warning (10036): Verilog HDL or VHDL warning at mult.vhd(20): object \"i\" assigned a value but never read" {  } { { "mult.vhd" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/mult.vhd" 20 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "xa mult.vhd(24) " "Warning (10492): VHDL Process Statement warning at mult.vhd(24): signal \"xa\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult.vhd" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/mult.vhd" 24 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "xb mult.vhd(24) " "Warning (10492): VHDL Process Statement warning at mult.vhd(24): signal \"xb\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult.vhd" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/mult.vhd" 24 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "xa mult.vhd(28) " "Warning (10492): VHDL Process Statement warning at mult.vhd(28): signal \"xa\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult.vhd" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/mult.vhd" 28 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "xb mult.vhd(28) " "Warning (10492): VHDL Process Statement warning at mult.vhd(28): signal \"xb\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult.vhd" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/mult.vhd" 28 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "xa mult.vhd(32) " "Warning (10492): VHDL Process Statement warning at mult.vhd(32): signal \"xa\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult.vhd" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/mult.vhd" 32 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "xb mult.vhd(32) " "Warning (10492): VHDL Process Statement warning at mult.vhd(32): signal \"xb\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult.vhd" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/mult.vhd" 32 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "xa mult.vhd(36) " "Warning (10492): VHDL Process Statement warning at mult.vhd(36): signal \"xa\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult.vhd" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/mult.vhd" 36 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "xb mult.vhd(36) " "Warning (10492): VHDL Process Statement warning at mult.vhd(36): signal \"xb\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult.vhd" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/mult.vhd" 36 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "xa mult.vhd(40) " "Warning (10492): VHDL Process Statement warning at mult.vhd(40): signal \"xa\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult.vhd" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/mult.vhd" 40 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "xb mult.vhd(40) " "Warning (10492): VHDL Process Statement warning at mult.vhd(40): signal \"xb\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult.vhd" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/mult.vhd" 40 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "xa mult.vhd(44) " "Warning (10492): VHDL Process Statement warning at mult.vhd(44): signal \"xa\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult.vhd" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/mult.vhd" 44 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "xb mult.vhd(44) " "Warning (10492): VHDL Process Statement warning at mult.vhd(44): signal \"xb\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult.vhd" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/mult.vhd" 44 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "xa mult.vhd(48) " "Warning (10492): VHDL Process Statement warning at mult.vhd(48): signal \"xa\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult.vhd" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/mult.vhd" 48 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "xb mult.vhd(48) " "Warning (10492): VHDL Process Statement warning at mult.vhd(48): signal \"xb\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult.vhd" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/mult.vhd" 48 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "xa mult.vhd(52) " "Warning (10492): VHDL Process Statement warning at mult.vhd(52): signal \"xa\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult.vhd" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/mult.vhd" 52 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "xb mult.vhd(52) " "Warning (10492): VHDL Process Statement warning at mult.vhd(52): signal \"xb\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mult.vhd" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/mult.vhd" 52 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "tran8to9:inst\|b\[0\] data_in GND " "Warning: Reduced register \"tran8to9:inst\|b\[0\]\" with stuck data_in port to stuck value GND" {  } { { "tran8to9.vhd" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/tran8to9.vhd" 20 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "tran8to9:inst\|a\[8\] data_in GND " "Warning: Reduced register \"tran8to9:inst\|a\[8\]\" with stuck data_in port to stuck value GND" {  } { { "tran8to9.vhd" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/tran8to9.vhd" 20 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "adder10:inst10\|reg1\[1\] data_in GND " "Warning: Reduced register \"adder10:inst10\|reg1\[1\]\" with stuck data_in port to stuck value GND" {  } { { "adder10.vhd" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/adder10.vhd" 26 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "adder10:inst10\|reg1\[16\] data_in GND " "Warning: Reduced register \"adder10:inst10\|reg1\[16\]\" with stuck data_in port to stuck value GND" {  } { { "adder10.vhd" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/adder10.vhd" 26 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "tran8to9:inst3\|b\[0\] data_in GND " "Warning: Reduced register \"tran8to9:inst3\|b\[0\]\" with stuck data_in port to stuck value GND" {  } { { "tran8to9.vhd" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/tran8to9.vhd" 20 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "tran8to9:inst3\|a\[8\] data_in GND " "Warning: Reduced register \"tran8to9:inst3\|a\[8\]\" with stuck data_in port to stuck value GND" {  } { { "tran8to9.vhd" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/tran8to9.vhd" 20 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "adder10:inst9\|reg1\[1\] data_in GND " "Warning: Reduced register \"adder10:inst9\|reg1\[1\]\" with stuck data_in port to stuck value GND" {  } { { "adder10.vhd" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/adder10.vhd" 26 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}