adder.map.qmsg

采用加法树流水线乘法构造八位乘法器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 02 14:08:38 2009 " "Info: Processing started: Thu Apr 02 14:08:38 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off adder -c adder " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off adder -c adder" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "add.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file add.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 add " "Info: Found entity 1: add" {  } { { "add.bdf" "" { Schematic "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/add.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "add " "Info: Elaborating entity \"add\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "rst adder16 inst13 " "Warning: Port \"rst\" of type adder16 and instance \"inst13\" is missing source signal" {  } { { "add.bdf" "" { Schematic "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/add.bdf" { { 168 984 1128 296 "inst13" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "rst adder13 inst1 " "Warning: Port \"rst\" of type adder13 and instance \"inst1\" is missing source signal" {  } { { "add.bdf" "" { Schematic "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/add.bdf" { { 56 816 960 184 "inst1" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "rst adder10 inst7 " "Warning: Port \"rst\" of type adder10 and instance \"inst7\" is missing source signal" {  } { { "add.bdf" "" { Schematic "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/add.bdf" { { 8 496 632 136 "inst7" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "rst adder10 inst8 " "Warning: Port \"rst\" of type adder10 and instance \"inst8\" is missing source signal" {  } { { "add.bdf" "" { Schematic "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/add.bdf" { { 136 496 632 264 "inst8" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "rst adder13 inst12 " "Warning: Port \"rst\" of type adder13 and instance \"inst12\" is missing source signal" {  } { { "add.bdf" "" { Schematic "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/add.bdf" { { 320 816 960 448 "inst12" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "rst adder10 inst9 " "Warning: Port \"rst\" of type adder10 and instance \"inst9\" is missing source signal" {  } { { "add.bdf" "" { Schematic "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/add.bdf" { { 264 496 632 392 "inst9" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "rst adder10 inst10 " "Warning: Port \"rst\" of type adder10 and instance \"inst10\" is missing source signal" {  } { { "add.bdf" "" { Schematic "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/add.bdf" { { 392 496 632 520 "inst10" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "adder16.vhd 2 1 " "Warning: Using design file adder16.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 adder16-depict " "Info: Found design unit 1: adder16-depict" {  } { { "adder16.vhd" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/adder16.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 adder16 " "Info: Found entity 1: adder16" {  } { { "adder16.vhd" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/adder16.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "adder16 adder16:inst13 " "Info: Elaborating entity \"adder16\" for hierarchy \"adder16:inst13\"" {  } { { "add.bdf" "inst13" { Schematic "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/add.bdf" { { 168 984 1128 296 "inst13" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "tran13to16.vhd 2 1 " "Warning: Using design file tran13to16.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 tran13to16-beha " "Info: Found design unit 1: tran13to16-beha" {  } { { "tran13to16.vhd" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/tran13to16.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 tran13to16 " "Info: Found entity 1: tran13to16" {  } { { "tran13to16.vhd" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/tran13to16.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tran13to16 tran13to16:inst14 " "Info: Elaborating entity \"tran13to16\" for hierarchy \"tran13to16:inst14\"" {  } { { "add.bdf" "inst14" { Schematic "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/add.bdf" { { 200 752 904 296 "inst14" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "adder13.vhd 2 1 " "Warning: Using design file adder13.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 adder13-depict " "Info: Found design unit 1: adder13-depict" {  } { { "adder13.vhd" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/adder13.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 adder13 " "Info: Found entity 1: adder13" {  } { { "adder13.vhd" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/adder13.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "adder13 adder13:inst1 " "Info: Elaborating entity \"adder13\" for hierarchy \"adder13:inst1\"" {  } { { "add.bdf" "inst1" { Schematic "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/add.bdf" { { 56 816 960 184 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "tran10to12.vhd 2 1 " "Warning: Using design file tran10to12.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 tran10to12-beha " "Info: Found design unit 1: tran10to12-beha" {  } { { "tran10to12.vhd" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/tran10to12.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 tran10to12 " "Info: Found entity 1: tran10to12" {  } { { "tran10to12.vhd" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/tran10to12.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tran10to12 tran10to12:inst6 " "Info: Elaborating entity \"tran10to12\" for hierarchy \"tran10to12:inst6\"" {  } { { "add.bdf" "inst6" { Schematic "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/add.bdf" { { 88 656 800 184 "inst6" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "adder10.vhd 2 1 " "Warning: Using design file adder10.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 adder10-depict " "Info: Found design unit 1: adder10-depict" {  } { { "adder10.vhd" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/adder10.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 adder10 " "Info: Found entity 1: adder10" {  } { { "adder10.vhd" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/adder10.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "adder10 adder10:inst7 " "Info: Elaborating entity \"adder10\" for hierarchy \"adder10:inst7\"" {  } { { "add.bdf" "inst7" { Schematic "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/add.bdf" { { 8 496 632 136 "inst7" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "reg4 adder10.vhd(74) " "Warning (10631): VHDL Process Statement warning at adder10.vhd(74): inferring latch(es) for signal or variable \"reg4\", which holds its previous value in one or more paths through the process" {  } { { "adder10.vhd" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/adder10.vhd" 74 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "reg4\[4\] adder10.vhd(74) " "Info (10041): Verilog HDL or VHDL info at adder10.vhd(74): inferred latch for \"reg4\[4\]\"" {  } { { "adder10.vhd" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/adder10.vhd" 74 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "tran8to9.vhd 2 1 " "Warning: Using design file tran8to9.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 tran8to9-beha " "Info: Found design unit 1: tran8to9-beha" {  } { { "tran8to9.vhd" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/tran8to9.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 tran8to9 " "Info: Found entity 1: tran8to9" {  } { { "tran8to9.vhd" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/tran8to9.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tran8to9 tran8to9:inst4 " "Info: Elaborating entity \"tran8to9\" for hierarchy \"tran8to9:inst4\"" {  } { { "add.bdf" "inst4" { Schematic "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/add.bdf" { { 48 336 464 144 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}