adder.fit.qmsg

采用加法树流水线乘法构造八位乘法器

{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "33 unused 3.30 17 16 0 " "Info: Number of I/O pins in group: 33 (unused VREF, 3.30 VCCIO, 17 input, 16 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0 0 "I/O standards used: %1!s!" 0 0}  } {  } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0}  } {  } 0 0 "Statistics of %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 1 84 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  84 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 2 77 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used --  77 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 72 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  72 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 74 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  74 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use unused 0 85 " "Info: I/O bank number 5 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  85 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use unused 1 80 " "Info: I/O bank number 6 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  80 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use unused 0 74 " "Info: I/O bank number 7 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  74 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use unused 0 72 " "Info: I/O bank number 8 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  72 pins available" {  } {  } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0}  } {  } 0 0 "Statistics of %1!s!" 0 0}  } {  } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.034 ns register register " "Info: Estimated most critical path is register to register delay of 3.034 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns adder13:inst1\|altshift_taps:reg3_rtl_10\|shift_taps_r1m:auto_generated\|cntr_9oc:cntr1\|safe_q\[0\] 1 REG LAB_X54_Y20 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X54_Y20; Fanout = 7; REG Node = 'adder13:inst1\|altshift_taps:reg3_rtl_10\|shift_taps_r1m:auto_generated\|cntr_9oc:cntr1\|safe_q\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { adder13:inst1|altshift_taps:reg3_rtl_10|shift_taps_r1m:auto_generated|cntr_9oc:cntr1|safe_q[0] } "NODE_NAME" } } { "db/cntr_9oc.tdf" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/db/cntr_9oc.tdf" 73 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.455 ns) + CELL(0.414 ns) 0.869 ns adder13:inst1\|altshift_taps:reg3_rtl_10\|shift_taps_r1m:auto_generated\|cntr_9oc:cntr1\|counter_comb_bita0~COUT 2 COMB LAB_X54_Y20 2 " "Info: 2: + IC(0.455 ns) + CELL(0.414 ns) = 0.869 ns; Loc. = LAB_X54_Y20; Fanout = 2; COMB Node = 'adder13:inst1\|altshift_taps:reg3_rtl_10\|shift_taps_r1m:auto_generated\|cntr_9oc:cntr1\|counter_comb_bita0~COUT'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.869 ns" { adder13:inst1|altshift_taps:reg3_rtl_10|shift_taps_r1m:auto_generated|cntr_9oc:cntr1|safe_q[0] adder13:inst1|altshift_taps:reg3_rtl_10|shift_taps_r1m:auto_generated|cntr_9oc:cntr1|counter_comb_bita0~COUT } "NODE_NAME" } } { "db/cntr_9oc.tdf" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/db/cntr_9oc.tdf" 34 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 0.940 ns adder13:inst1\|altshift_taps:reg3_rtl_10\|shift_taps_r1m:auto_generated\|cntr_9oc:cntr1\|counter_comb_bita1~COUT 3 COMB LAB_X54_Y20 2 " "Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 0.940 ns; Loc. = LAB_X54_Y20; Fanout = 2; COMB Node = 'adder13:inst1\|altshift_taps:reg3_rtl_10\|shift_taps_r1m:auto_generated\|cntr_9oc:cntr1\|counter_comb_bita1~COUT'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { adder13:inst1|altshift_taps:reg3_rtl_10|shift_taps_r1m:auto_generated|cntr_9oc:cntr1|counter_comb_bita0~COUT adder13:inst1|altshift_taps:reg3_rtl_10|shift_taps_r1m:auto_generated|cntr_9oc:cntr1|counter_comb_bita1~COUT } "NODE_NAME" } } { "db/cntr_9oc.tdf" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/db/cntr_9oc.tdf" 39 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.011 ns adder13:inst1\|altshift_taps:reg3_rtl_10\|shift_taps_r1m:auto_generated\|cntr_9oc:cntr1\|counter_comb_bita2~COUT 4 COMB LAB_X54_Y20 2 " "Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 1.011 ns; Loc. = LAB_X54_Y20; Fanout = 2; COMB Node = 'adder13:inst1\|altshift_taps:reg3_rtl_10\|shift_taps_r1m:auto_generated\|cntr_9oc:cntr1\|counter_comb_bita2~COUT'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { adder13:inst1|altshift_taps:reg3_rtl_10|shift_taps_r1m:auto_generated|cntr_9oc:cntr1|counter_comb_bita1~COUT adder13:inst1|altshift_taps:reg3_rtl_10|shift_taps_r1m:auto_generated|cntr_9oc:cntr1|counter_comb_bita2~COUT } "NODE_NAME" } } { "db/cntr_9oc.tdf" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/db/cntr_9oc.tdf" 44 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.082 ns adder13:inst1\|altshift_taps:reg3_rtl_10\|shift_taps_r1m:auto_generated\|cntr_9oc:cntr1\|counter_comb_bita3~COUT 5 COMB LAB_X54_Y20 2 " "Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 1.082 ns; Loc. = LAB_X54_Y20; Fanout = 2; COMB Node = 'adder13:inst1\|altshift_taps:reg3_rtl_10\|shift_taps_r1m:auto_generated\|cntr_9oc:cntr1\|counter_comb_bita3~COUT'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { adder13:inst1|altshift_taps:reg3_rtl_10|shift_taps_r1m:auto_generated|cntr_9oc:cntr1|counter_comb_bita2~COUT adder13:inst1|altshift_taps:reg3_rtl_10|shift_taps_r1m:auto_generated|cntr_9oc:cntr1|counter_comb_bita3~COUT } "NODE_NAME" } } { "db/cntr_9oc.tdf" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/db/cntr_9oc.tdf" 49 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.153 ns adder13:inst1\|altshift_taps:reg3_rtl_10\|shift_taps_r1m:auto_generated\|cntr_9oc:cntr1\|counter_comb_bita4~COUT 6 COMB LAB_X54_Y20 1 " "Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 1.153 ns; Loc. = LAB_X54_Y20; Fanout = 1; COMB Node = 'adder13:inst1\|altshift_taps:reg3_rtl_10\|shift_taps_r1m:auto_generated\|cntr_9oc:cntr1\|counter_comb_bita4~COUT'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { adder13:inst1|altshift_taps:reg3_rtl_10|shift_taps_r1m:auto_generated|cntr_9oc:cntr1|counter_comb_bita3~COUT adder13:inst1|altshift_taps:reg3_rtl_10|shift_taps_r1m:auto_generated|cntr_9oc:cntr1|counter_comb_bita4~COUT } "NODE_NAME" } } { "db/cntr_9oc.tdf" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/db/cntr_9oc.tdf" 54 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 1.563 ns adder13:inst1\|altshift_taps:reg3_rtl_10\|shift_taps_r1m:auto_generated\|cntr_9oc:cntr1\|counter_comb_bita4~9 7 COMB LAB_X54_Y20 1 " "Info: 7: + IC(0.000 ns) + CELL(0.410 ns) = 1.563 ns; Loc. = LAB_X54_Y20; Fanout = 1; COMB Node = 'adder13:inst1\|altshift_taps:reg3_rtl_10\|shift_taps_r1m:auto_generated\|cntr_9oc:cntr1\|counter_comb_bita4~9'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.410 ns" { adder13:inst1|altshift_taps:reg3_rtl_10|shift_taps_r1m:auto_generated|cntr_9oc:cntr1|counter_comb_bita4~COUT adder13:inst1|altshift_taps:reg3_rtl_10|shift_taps_r1m:auto_generated|cntr_9oc:cntr1|counter_comb_bita4~9 } "NODE_NAME" } } { "db/cntr_9oc.tdf" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/db/cntr_9oc.tdf" 54 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.127 ns) + CELL(0.438 ns) 2.128 ns adder13:inst1\|altshift_taps:reg3_rtl_10\|shift_taps_r1m:auto_generated\|cntr_9oc:cntr1\|cout_actual 8 COMB LAB_X54_Y20 5 " "Info: 8: + IC(0.127 ns) + CELL(0.438 ns) = 2.128 ns; Loc. = LAB_X54_Y20; Fanout = 5; COMB Node = 'adder13:inst1\|altshift_taps:reg3_rtl_10\|shift_taps_r1m:auto_generated\|cntr_9oc:cntr1\|cout_actual'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.565 ns" { adder13:inst1|altshift_taps:reg3_rtl_10|shift_taps_r1m:auto_generated|cntr_9oc:cntr1|counter_comb_bita4~9 adder13:inst1|altshift_taps:reg3_rtl_10|shift_taps_r1m:auto_generated|cntr_9oc:cntr1|cout_actual } "NODE_NAME" } } { "db/cntr_9oc.tdf" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/db/cntr_9oc.tdf" 67 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.247 ns) + CELL(0.659 ns) 3.034 ns adder13:inst1\|altshift_taps:reg3_rtl_10\|shift_taps_r1m:auto_generated\|cntr_9oc:cntr1\|safe_q\[0\] 9 REG LAB_X54_Y20 7 " "Info: 9: + IC(0.247 ns) + CELL(0.659 ns) = 3.034 ns; Loc. = LAB_X54_Y20; Fanout = 7; REG Node = 'adder13:inst1\|altshift_taps:reg3_rtl_10\|shift_taps_r1m:auto_generated\|cntr_9oc:cntr1\|safe_q\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.906 ns" { adder13:inst1|altshift_taps:reg3_rtl_10|shift_taps_r1m:auto_generated|cntr_9oc:cntr1|cout_actual adder13:inst1|altshift_taps:reg3_rtl_10|shift_taps_r1m:auto_generated|cntr_9oc:cntr1|safe_q[0] } "NODE_NAME" } } { "db/cntr_9oc.tdf" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/db/cntr_9oc.tdf" 73 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.205 ns ( 72.68 % ) " "Info: Total cell delay = 2.205 ns ( 72.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.829 ns ( 27.32 % ) " "Info: Total interconnect delay = 0.829 ns ( 27.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.034 ns" { adder13:inst1|altshift_taps:reg3_rtl_10|shift_taps_r1m:auto_generated|cntr_9oc:cntr1|safe_q[0] adder13:inst1|altshift_taps:reg3_rtl_10|shift_taps_r1m:auto_generated|cntr_9oc:cntr1|counter_comb_bita0~COUT adder13:inst1|altshift_taps:reg3_rtl_10|shift_taps_r1m:auto_generated|cntr_9oc:cntr1|counter_comb_bita1~COUT adder13:inst1|altshift_taps:reg3_rtl_10|shift_taps_r1m:auto_generated|cntr_9oc:cntr1|counter_comb_bita2~COUT adder13:inst1|altshift_taps:reg3_rtl_10|shift_taps_r1m:auto_generated|cntr_9oc:cntr1|counter_comb_bita3~COUT adder13:inst1|altshift_taps:reg3_rtl_10|shift_taps_r1m:auto_generated|cntr_9oc:cntr1|counter_comb_bita4~COUT adder13:inst1|altshift_taps:reg3_rtl_10|shift_taps_r1m:auto_generated|cntr_9oc:cntr1|counter_comb_bita4~9 adder13:inst1|altshift_taps:reg3_rtl_10|shift_taps_r1m:auto_generated|cntr_9oc:cntr1|cout_actual adder13:inst1|altshift_taps:reg3_rtl_10|shift_taps_r1m:auto_generated|cntr_9oc:cntr1|safe_q[0] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}