adder.tan.qmsg

采用加法树流水线乘法构造八位乘法器

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk memory memory adder16:inst13\|altshift_taps:reg5_rtl_7\|shift_taps_b3m:auto_generated\|altsyncram_ic81:altsyncram2\|ram_block3a0~portb_address_reg1 adder16:inst13\|altshift_taps:reg5_rtl_7\|shift_taps_b3m:auto_generated\|altsyncram_ic81:altsyncram2\|q_b\[7\] 235.07 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 235.07 MHz between source memory \"adder16:inst13\|altshift_taps:reg5_rtl_7\|shift_taps_b3m:auto_generated\|altsyncram_ic81:altsyncram2\|ram_block3a0~portb_address_reg1\" and destination memory \"adder16:inst13\|altshift_taps:reg5_rtl_7\|shift_taps_b3m:auto_generated\|altsyncram_ic81:altsyncram2\|q_b\[7\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.127 ns 2.127 ns 4.254 ns " "Info: fmax restricted to Clock High delay (2.127 ns) plus Clock Low delay (2.127 ns) : restricted to 4.254 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.892 ns + Longest memory memory " "Info: + Longest memory to memory delay is 2.892 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns adder16:inst13\|altshift_taps:reg5_rtl_7\|shift_taps_b3m:auto_generated\|altsyncram_ic81:altsyncram2\|ram_block3a0~portb_address_reg1 1 MEM M4K_X55_Y24 17 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X55_Y24; Fanout = 17; MEM Node = 'adder16:inst13\|altshift_taps:reg5_rtl_7\|shift_taps_b3m:auto_generated\|altsyncram_ic81:altsyncram2\|ram_block3a0~portb_address_reg1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { adder16:inst13|altshift_taps:reg5_rtl_7|shift_taps_b3m:auto_generated|altsyncram_ic81:altsyncram2|ram_block3a0~portb_address_reg1 } "NODE_NAME" } } { "db/altsyncram_ic81.tdf" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/db/altsyncram_ic81.tdf" 47 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.892 ns) 2.892 ns adder16:inst13\|altshift_taps:reg5_rtl_7\|shift_taps_b3m:auto_generated\|altsyncram_ic81:altsyncram2\|q_b\[7\] 2 MEM M4K_X55_Y24 2 " "Info: 2: + IC(0.000 ns) + CELL(2.892 ns) = 2.892 ns; Loc. = M4K_X55_Y24; Fanout = 2; MEM Node = 'adder16:inst13\|altshift_taps:reg5_rtl_7\|shift_taps_b3m:auto_generated\|altsyncram_ic81:altsyncram2\|q_b\[7\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.892 ns" { adder16:inst13|altshift_taps:reg5_rtl_7|shift_taps_b3m:auto_generated|altsyncram_ic81:altsyncram2|ram_block3a0~portb_address_reg1 adder16:inst13|altshift_taps:reg5_rtl_7|shift_taps_b3m:auto_generated|altsyncram_ic81:altsyncram2|q_b[7] } "NODE_NAME" } } { "db/altsyncram_ic81.tdf" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/db/altsyncram_ic81.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.892 ns ( 100.00 % ) " "Info: Total cell delay = 2.892 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.892 ns" { adder16:inst13|altshift_taps:reg5_rtl_7|shift_taps_b3m:auto_generated|altsyncram_ic81:altsyncram2|ram_block3a0~portb_address_reg1 adder16:inst13|altshift_taps:reg5_rtl_7|shift_taps_b3m:auto_generated|altsyncram_ic81:altsyncram2|q_b[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.892 ns" { adder16:inst13|altshift_taps:reg5_rtl_7|shift_taps_b3m:auto_generated|altsyncram_ic81:altsyncram2|ram_block3a0~portb_address_reg1 adder16:inst13|altshift_taps:reg5_rtl_7|shift_taps_b3m:auto_generated|altsyncram_ic81:altsyncram2|q_b[7] } { 0.000ns 0.000ns } { 0.000ns 2.892ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.053 ns - Smallest " "Info: - Smallest clock skew is -0.053 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.912 ns + Shortest memory " "Info: + Shortest clock path from clock \"clk\" to destination memory is 2.912 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_T2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_T2; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "add.bdf" "" { Schematic "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/add.bdf" { { 136 -16 152 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.114 ns) + CELL(0.000 ns) 1.103 ns clk~clkctrl 2 COMB CLKCTRL_G3 671 " "Info: 2: + IC(0.114 ns) + CELL(0.000 ns) = 1.103 ns; Loc. = CLKCTRL_G3; Fanout = 671; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.114 ns" { clk clk~clkctrl } "NODE_NAME" } } { "add.bdf" "" { Schematic "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/add.bdf" { { 136 -16 152 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.173 ns) + CELL(0.636 ns) 2.912 ns adder16:inst13\|altshift_taps:reg5_rtl_7\|shift_taps_b3m:auto_generated\|altsyncram_ic81:altsyncram2\|q_b\[7\] 3 MEM M4K_X55_Y24 2 " "Info: 3: + IC(1.173 ns) + CELL(0.636 ns) = 2.912 ns; Loc. = M4K_X55_Y24; Fanout = 2; MEM Node = 'adder16:inst13\|altshift_taps:reg5_rtl_7\|shift_taps_b3m:auto_generated\|altsyncram_ic81:altsyncram2\|q_b\[7\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.809 ns" { clk~clkctrl adder16:inst13|altshift_taps:reg5_rtl_7|shift_taps_b3m:auto_generated|altsyncram_ic81:altsyncram2|q_b[7] } "NODE_NAME" } } { "db/altsyncram_ic81.tdf" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/db/altsyncram_ic81.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.625 ns ( 55.80 % ) " "Info: Total cell delay = 1.625 ns ( 55.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.287 ns ( 44.20 % ) " "Info: Total interconnect delay = 1.287 ns ( 44.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.912 ns" { clk clk~clkctrl adder16:inst13|altshift_taps:reg5_rtl_7|shift_taps_b3m:auto_generated|altsyncram_ic81:altsyncram2|q_b[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.912 ns" { clk clk~combout clk~clkctrl adder16:inst13|altshift_taps:reg5_rtl_7|shift_taps_b3m:auto_generated|altsyncram_ic81:altsyncram2|q_b[7] } { 0.000ns 0.000ns 0.114ns 1.173ns } { 0.000ns 0.989ns 0.000ns 0.636ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.965 ns - Longest memory " "Info: - Longest clock path from clock \"clk\" to source memory is 2.965 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_T2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_T2; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "add.bdf" "" { Schematic "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/add.bdf" { { 136 -16 152 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.114 ns) + CELL(0.000 ns) 1.103 ns clk~clkctrl 2 COMB CLKCTRL_G3 671 " "Info: 2: + IC(0.114 ns) + CELL(0.000 ns) = 1.103 ns; Loc. = CLKCTRL_G3; Fanout = 671; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.114 ns" { clk clk~clkctrl } "NODE_NAME" } } { "add.bdf" "" { Schematic "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/add.bdf" { { 136 -16 152 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.173 ns) + CELL(0.689 ns) 2.965 ns adder16:inst13\|altshift_taps:reg5_rtl_7\|shift_taps_b3m:auto_generated\|altsyncram_ic81:altsyncram2\|ram_block3a0~portb_address_reg1 3 MEM M4K_X55_Y24 17 " "Info: 3: + IC(1.173 ns) + CELL(0.689 ns) = 2.965 ns; Loc. = M4K_X55_Y24; Fanout = 17; MEM Node = 'adder16:inst13\|altshift_taps:reg5_rtl_7\|shift_taps_b3m:auto_generated\|altsyncram_ic81:altsyncram2\|ram_block3a0~portb_address_reg1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.862 ns" { clk~clkctrl adder16:inst13|altshift_taps:reg5_rtl_7|shift_taps_b3m:auto_generated|altsyncram_ic81:altsyncram2|ram_block3a0~portb_address_reg1 } "NODE_NAME" } } { "db/altsyncram_ic81.tdf" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/db/altsyncram_ic81.tdf" 47 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.678 ns ( 56.59 % ) " "Info: Total cell delay = 1.678 ns ( 56.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.287 ns ( 43.41 % ) " "Info: Total interconnect delay = 1.287 ns ( 43.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.965 ns" { clk clk~clkctrl adder16:inst13|altshift_taps:reg5_rtl_7|shift_taps_b3m:auto_generated|altsyncram_ic81:altsyncram2|ram_block3a0~portb_address_reg1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.965 ns" { clk clk~combout clk~clkctrl adder16:inst13|altshift_taps:reg5_rtl_7|shift_taps_b3m:auto_generated|altsyncram_ic81:altsyncram2|ram_block3a0~portb_address_reg1 } { 0.000ns 0.000ns 0.114ns 1.173ns } { 0.000ns 0.989ns 0.000ns 0.689ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.912 ns" { clk clk~clkctrl adder16:inst13|altshift_taps:reg5_rtl_7|shift_taps_b3m:auto_generated|altsyncram_ic81:altsyncram2|q_b[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.912 ns" { clk clk~combout clk~clkctrl adder16:inst13|altshift_taps:reg5_rtl_7|shift_taps_b3m:auto_generated|altsyncram_ic81:altsyncram2|q_b[7] } { 0.000ns 0.000ns 0.114ns 1.173ns } { 0.000ns 0.989ns 0.000ns 0.636ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.965 ns" { clk clk~clkctrl adder16:inst13|altshift_taps:reg5_rtl_7|shift_taps_b3m:auto_generated|altsyncram_ic81:altsyncram2|ram_block3a0~portb_address_reg1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.965 ns" { clk clk~combout clk~clkctrl adder16:inst13|altshift_taps:reg5_rtl_7|shift_taps_b3m:auto_generated|altsyncram_ic81:altsyncram2|ram_block3a0~portb_address_reg1 } { 0.000ns 0.000ns 0.114ns 1.173ns } { 0.000ns 0.989ns 0.000ns 0.689ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.209 ns + " "Info: + Micro clock to output delay of source is 0.209 ns" {  } { { "db/altsyncram_ic81.tdf" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/db/altsyncram_ic81.tdf" 47 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.035 ns + " "Info: + Micro setup delay of destination is 0.035 ns" {  } { { "db/altsyncram_ic81.tdf" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/db/altsyncram_ic81.tdf" 43 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.892 ns" { adder16:inst13|altshift_taps:reg5_rtl_7|shift_taps_b3m:auto_generated|altsyncram_ic81:altsyncram2|ram_block3a0~portb_address_reg1 adder16:inst13|altshift_taps:reg5_rtl_7|shift_taps_b3m:auto_generated|altsyncram_ic81:altsyncram2|q_b[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.892 ns" { adder16:inst13|altshift_taps:reg5_rtl_7|shift_taps_b3m:auto_generated|altsyncram_ic81:altsyncram2|ram_block3a0~portb_address_reg1 adder16:inst13|altshift_taps:reg5_rtl_7|shift_taps_b3m:auto_generated|altsyncram_ic81:altsyncram2|q_b[7] } { 0.000ns 0.000ns } { 0.000ns 2.892ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.912 ns" { clk clk~clkctrl adder16:inst13|altshift_taps:reg5_rtl_7|shift_taps_b3m:auto_generated|altsyncram_ic81:altsyncram2|q_b[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.912 ns" { clk clk~combout clk~clkctrl adder16:inst13|altshift_taps:reg5_rtl_7|shift_taps_b3m:auto_generated|altsyncram_ic81:altsyncram2|q_b[7] } { 0.000ns 0.000ns 0.114ns 1.173ns } { 0.000ns 0.989ns 0.000ns 0.636ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.965 ns" { clk clk~clkctrl adder16:inst13|altshift_taps:reg5_rtl_7|shift_taps_b3m:auto_generated|altsyncram_ic81:altsyncram2|ram_block3a0~portb_address_reg1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.965 ns" { clk clk~combout clk~clkctrl adder16:inst13|altshift_taps:reg5_rtl_7|shift_taps_b3m:auto_generated|altsyncram_ic81:altsyncram2|ram_block3a0~portb_address_reg1 } { 0.000ns 0.000ns 0.114ns 1.173ns } { 0.000ns 0.989ns 0.000ns 0.689ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { adder16:inst13|altshift_taps:reg5_rtl_7|shift_taps_b3m:auto_generated|altsyncram_ic81:altsyncram2|q_b[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { adder16:inst13|altshift_taps:reg5_rtl_7|shift_taps_b3m:auto_generated|altsyncram_ic81:altsyncram2|q_b[7] } { 0.000ns } { 0.088ns } } } { "db/altsyncram_ic81.tdf" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/db/altsyncram_ic81.tdf" 43 2 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "adder16:inst13\|altshift_taps:reg12_rtl_1\|shift_taps_e0m:auto_generated\|altsyncram_k681:altsyncram2\|ram_block3a0~porta_datain_reg1 xb\[6\] clk 5.820 ns memory " "Info: tsu for memory \"adder16:inst13\|altshift_taps:reg12_rtl_1\|shift_taps_e0m:auto_generated\|altsyncram_k681:altsyncram2\|ram_block3a0~porta_datain_reg1\" (data pin = \"xb\[6\]\", clock pin = \"clk\") is 5.820 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.721 ns + Longest pin memory " "Info: + Longest pin to memory delay is 8.721 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.850 ns) 0.850 ns xb\[6\] 1 PIN PIN_AK17 8 " "Info: 1: + IC(0.000 ns) + CELL(0.850 ns) = 0.850 ns; Loc. = PIN_AK17; Fanout = 8; PIN Node = 'xb\[6\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { xb[6] } "NODE_NAME" } } { "add.bdf" "" { Schematic "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/add.bdf" { { 184 -16 152 200 "xb\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.275 ns) + CELL(0.413 ns) 7.538 ns mult:inst2\|p6\[4\] 2 COMB LCCOMB_X57_Y25_N6 1 " "Info: 2: + IC(6.275 ns) + CELL(0.413 ns) = 7.538 ns; Loc. = LCCOMB_X57_Y25_N6; Fanout = 1; COMB Node = 'mult:inst2\|p6\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.688 ns" { xb[6] mult:inst2|p6[4] } "NODE_NAME" } } { "mult.vhd" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/mult.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.077 ns) + CELL(0.106 ns) 8.721 ns adder16:inst13\|altshift_taps:reg12_rtl_1\|shift_taps_e0m:auto_generated\|altsyncram_k681:altsyncram2\|ram_block3a0~porta_datain_reg1 3 MEM M4K_X55_Y26 1 " "Info: 3: + IC(1.077 ns) + CELL(0.106 ns) = 8.721 ns; Loc. = M4K_X55_Y26; Fanout = 1; MEM Node = 'adder16:inst13\|altshift_taps:reg12_rtl_1\|shift_taps_e0m:auto_generated\|altsyncram_k681:altsyncram2\|ram_block3a0~porta_datain_reg1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.183 ns" { mult:inst2|p6[4] adder16:inst13|altshift_taps:reg12_rtl_1|shift_taps_e0m:auto_generated|altsyncram_k681:altsyncram2|ram_block3a0~porta_datain_reg1 } "NODE_NAME" } } { "db/altsyncram_k681.tdf" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/db/altsyncram_k681.tdf" 47 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.369 ns ( 15.70 % ) " "Info: Total cell delay = 1.369 ns ( 15.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.352 ns ( 84.30 % ) " "Info: Total interconnect delay = 7.352 ns ( 84.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.721 ns" { xb[6] mult:inst2|p6[4] adder16:inst13|altshift_taps:reg12_rtl_1|shift_taps_e0m:auto_generated|altsyncram_k681:altsyncram2|ram_block3a0~porta_datain_reg1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.721 ns" { xb[6] xb[6]~combout mult:inst2|p6[4] adder16:inst13|altshift_taps:reg12_rtl_1|shift_taps_e0m:auto_generated|altsyncram_k681:altsyncram2|ram_block3a0~porta_datain_reg1 } { 0.000ns 0.000ns 6.275ns 1.077ns } { 0.000ns 0.850ns 0.413ns 0.106ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.035 ns + " "Info: + Micro setup delay of destination is 0.035 ns" {  } { { "db/altsyncram_k681.tdf" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/db/altsyncram_k681.tdf" 47 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.936 ns - Shortest memory " "Info: - Shortest clock path from clock \"clk\" to destination memory is 2.936 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_T2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_T2; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "add.bdf" "" { Schematic "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/add.bdf" { { 136 -16 152 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.114 ns) + CELL(0.000 ns) 1.103 ns clk~clkctrl 2 COMB CLKCTRL_G3 671 " "Info: 2: + IC(0.114 ns) + CELL(0.000 ns) = 1.103 ns; Loc. = CLKCTRL_G3; Fanout = 671; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.114 ns" { clk clk~clkctrl } "NODE_NAME" } } { "add.bdf" "" { Schematic "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/add.bdf" { { 136 -16 152 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.173 ns) + CELL(0.660 ns) 2.936 ns adder16:inst13\|altshift_taps:reg12_rtl_1\|shift_taps_e0m:auto_generated\|altsyncram_k681:altsyncram2\|ram_block3a0~porta_datain_reg1 3 MEM M4K_X55_Y26 1 " "Info: 3: + IC(1.173 ns) + CELL(0.660 ns) = 2.936 ns; Loc. = M4K_X55_Y26; Fanout = 1; MEM Node = 'adder16:inst13\|altshift_taps:reg12_rtl_1\|shift_taps_e0m:auto_generated\|altsyncram_k681:altsyncram2\|ram_block3a0~porta_datain_reg1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.833 ns" { clk~clkctrl adder16:inst13|altshift_taps:reg12_rtl_1|shift_taps_e0m:auto_generated|altsyncram_k681:altsyncram2|ram_block3a0~porta_datain_reg1 } "NODE_NAME" } } { "db/altsyncram_k681.tdf" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/db/altsyncram_k681.tdf" 47 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.649 ns ( 56.16 % ) " "Info: Total cell delay = 1.649 ns ( 56.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.287 ns ( 43.84 % ) " "Info: Total interconnect delay = 1.287 ns ( 43.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.936 ns" { clk clk~clkctrl adder16:inst13|altshift_taps:reg12_rtl_1|shift_taps_e0m:auto_generated|altsyncram_k681:altsyncram2|ram_block3a0~porta_datain_reg1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.936 ns" { clk clk~combout clk~clkctrl adder16:inst13|altshift_taps:reg12_rtl_1|shift_taps_e0m:auto_generated|altsyncram_k681:altsyncram2|ram_block3a0~porta_datain_reg1 } { 0.000ns 0.000ns 0.114ns 1.173ns } { 0.000ns 0.989ns 0.000ns 0.660ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.721 ns" { xb[6] mult:inst2|p6[4] adder16:inst13|altshift_taps:reg12_rtl_1|shift_taps_e0m:auto_generated|altsyncram_k681:altsyncram2|ram_block3a0~porta_datain_reg1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.721 ns" { xb[6] xb[6]~combout mult:inst2|p6[4] adder16:inst13|altshift_taps:reg12_rtl_1|shift_taps_e0m:auto_generated|altsyncram_k681:altsyncram2|ram_block3a0~porta_datain_reg1 } { 0.000ns 0.000ns 6.275ns 1.077ns } { 0.000ns 0.850ns 0.413ns 0.106ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.936 ns" { clk clk~clkctrl adder16:inst13|altshift_taps:reg12_rtl_1|shift_taps_e0m:auto_generated|altsyncram_k681:altsyncram2|ram_block3a0~porta_datain_reg1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.936 ns" { clk clk~combout clk~clkctrl adder16:inst13|altshift_taps:reg12_rtl_1|shift_taps_e0m:auto_generated|altsyncram_k681:altsyncram2|ram_block3a0~porta_datain_reg1 } { 0.000ns 0.000ns 0.114ns 1.173ns } { 0.000ns 0.989ns 0.000ns 0.660ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk mult\[11\] adder16:inst13\|altshift_taps:reg12_rtl_1\|shift_taps_e0m:auto_generated\|altsyncram_k681:altsyncram2\|q_b\[0\] 8.863 ns memory " "Info: tco from clock \"clk\" to destination pin \"mult\[11\]\" through memory \"adder16:inst13\|altshift_taps:reg12_rtl_1\|shift_taps_e0m:auto_generated\|altsyncram_k681:altsyncram2\|q_b\[0\]\" is 8.863 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.912 ns + Longest memory " "Info: + Longest clock path from clock \"clk\" to source memory is 2.912 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_T2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_T2; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "add.bdf" "" { Schematic "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/add.bdf" { { 136 -16 152 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.114 ns) + CELL(0.000 ns) 1.103 ns clk~clkctrl 2 COMB CLKCTRL_G3 671 " "Info: 2: + IC(0.114 ns) + CELL(0.000 ns) = 1.103 ns; Loc. = CLKCTRL_G3; Fanout = 671; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.114 ns" { clk clk~clkctrl } "NODE_NAME" } } { "add.bdf" "" { Schematic "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/add.bdf" { { 136 -16 152 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.173 ns) + CELL(0.636 ns) 2.912 ns adder16:inst13\|altshift_taps:reg12_rtl_1\|shift_taps_e0m:auto_generated\|altsyncram_k681:altsyncram2\|q_b\[0\] 3 MEM M4K_X55_Y26 1 " "Info: 3: + IC(1.173 ns) + CELL(0.636 ns) = 2.912 ns; Loc. = M4K_X55_Y26; Fanout = 1; MEM Node = 'adder16:inst13\|altshift_taps:reg12_rtl_1\|shift_taps_e0m:auto_generated\|altsyncram_k681:altsyncram2\|q_b\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.809 ns" { clk~clkctrl adder16:inst13|altshift_taps:reg12_rtl_1|shift_taps_e0m:auto_generated|altsyncram_k681:altsyncram2|q_b[0] } "NODE_NAME" } } { "db/altsyncram_k681.tdf" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/db/altsyncram_k681.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.625 ns ( 55.80 % ) " "Info: Total cell delay = 1.625 ns ( 55.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.287 ns ( 44.20 % ) " "Info: Total interconnect delay = 1.287 ns ( 44.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.912 ns" { clk clk~clkctrl adder16:inst13|altshift_taps:reg12_rtl_1|shift_taps_e0m:auto_generated|altsyncram_k681:altsyncram2|q_b[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.912 ns" { clk clk~combout clk~clkctrl adder16:inst13|altshift_taps:reg12_rtl_1|shift_taps_e0m:auto_generated|altsyncram_k681:altsyncram2|q_b[0] } { 0.000ns 0.000ns 0.114ns 1.173ns } { 0.000ns 0.989ns 0.000ns 0.636ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.209 ns + " "Info: + Micro clock to output delay of source is 0.209 ns" {  } { { "db/altsyncram_k681.tdf" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/db/altsyncram_k681.tdf" 43 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.742 ns + Longest memory pin " "Info: + Longest memory to pin delay is 5.742 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.088 ns) 0.088 ns adder16:inst13\|altshift_taps:reg12_rtl_1\|shift_taps_e0m:auto_generated\|altsyncram_k681:altsyncram2\|q_b\[0\] 1 MEM M4K_X55_Y26 1 " "Info: 1: + IC(0.000 ns) + CELL(0.088 ns) = 0.088 ns; Loc. = M4K_X55_Y26; Fanout = 1; MEM Node = 'adder16:inst13\|altshift_taps:reg12_rtl_1\|shift_taps_e0m:auto_generated\|altsyncram_k681:altsyncram2\|q_b\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { adder16:inst13|altshift_taps:reg12_rtl_1|shift_taps_e0m:auto_generated|altsyncram_k681:altsyncram2|q_b[0] } "NODE_NAME" } } { "db/altsyncram_k681.tdf" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/db/altsyncram_k681.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.052 ns) + CELL(2.602 ns) 5.742 ns mult\[11\] 2 PIN PIN_T22 0 " "Info: 2: + IC(3.052 ns) + CELL(2.602 ns) = 5.742 ns; Loc. = PIN_T22; Fanout = 0; PIN Node = 'mult\[11\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.654 ns" { adder16:inst13|altshift_taps:reg12_rtl_1|shift_taps_e0m:auto_generated|altsyncram_k681:altsyncram2|q_b[0] mult[11] } "NODE_NAME" } } { "add.bdf" "" { Schematic "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/add.bdf" { { 192 1136 1312 208 "mult\[15..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.690 ns ( 46.85 % ) " "Info: Total cell delay = 2.690 ns ( 46.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.052 ns ( 53.15 % ) " "Info: Total interconnect delay = 3.052 ns ( 53.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.742 ns" { adder16:inst13|altshift_taps:reg12_rtl_1|shift_taps_e0m:auto_generated|altsyncram_k681:altsyncram2|q_b[0] mult[11] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.742 ns" { adder16:inst13|altshift_taps:reg12_rtl_1|shift_taps_e0m:auto_generated|altsyncram_k681:altsyncram2|q_b[0] mult[11] } { 0.000ns 3.052ns } { 0.088ns 2.602ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.912 ns" { clk clk~clkctrl adder16:inst13|altshift_taps:reg12_rtl_1|shift_taps_e0m:auto_generated|altsyncram_k681:altsyncram2|q_b[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.912 ns" { clk clk~combout clk~clkctrl adder16:inst13|altshift_taps:reg12_rtl_1|shift_taps_e0m:auto_generated|altsyncram_k681:altsyncram2|q_b[0] } { 0.000ns 0.000ns 0.114ns 1.173ns } { 0.000ns 0.989ns 0.000ns 0.636ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.742 ns" { adder16:inst13|altshift_taps:reg12_rtl_1|shift_taps_e0m:auto_generated|altsyncram_k681:altsyncram2|q_b[0] mult[11] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.742 ns" { adder16:inst13|altshift_taps:reg12_rtl_1|shift_taps_e0m:auto_generated|altsyncram_k681:altsyncram2|q_b[0] mult[11] } { 0.000ns 3.052ns } { 0.088ns 2.602ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "tran8to9:inst\|b\[1\] xa\[0\] clk -0.106 ns register " "Info: th for register \"tran8to9:inst\|b\[1\]\" (data pin = \"xa\[0\]\", clock pin = \"clk\") is -0.106 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.897 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.897 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_T2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_T2; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "add.bdf" "" { Schematic "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/add.bdf" { { 136 -16 152 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.114 ns) + CELL(0.000 ns) 1.103 ns clk~clkctrl 2 COMB CLKCTRL_G3 671 " "Info: 2: + IC(0.114 ns) + CELL(0.000 ns) = 1.103 ns; Loc. = CLKCTRL_G3; Fanout = 671; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.114 ns" { clk clk~clkctrl } "NODE_NAME" } } { "add.bdf" "" { Schematic "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/add.bdf" { { 136 -16 152 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.257 ns) + CELL(0.537 ns) 2.897 ns tran8to9:inst\|b\[1\] 3 REG LCFF_X58_Y24_N9 1 " "Info: 3: + IC(1.257 ns) + CELL(0.537 ns) = 2.897 ns; Loc. = LCFF_X58_Y24_N9; Fanout = 1; REG Node = 'tran8to9:inst\|b\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.794 ns" { clk~clkctrl tran8to9:inst|b[1] } "NODE_NAME" } } { "tran8to9.vhd" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/tran8to9.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 52.68 % ) " "Info: Total cell delay = 1.526 ns ( 52.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.371 ns ( 47.32 % ) " "Info: Total interconnect delay = 1.371 ns ( 47.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.897 ns" { clk clk~clkctrl tran8to9:inst|b[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.897 ns" { clk clk~combout clk~clkctrl tran8to9:inst|b[1] } { 0.000ns 0.000ns 0.114ns 1.257ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "tran8to9.vhd" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/tran8to9.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.269 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.269 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.959 ns) 0.959 ns xa\[0\] 1 PIN PIN_H15 8 " "Info: 1: + IC(0.000 ns) + CELL(0.959 ns) = 0.959 ns; Loc. = PIN_H15; Fanout = 8; PIN Node = 'xa\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { xa[0] } "NODE_NAME" } } { "add.bdf" "" { Schematic "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/add.bdf" { { 168 -16 152 184 "xa\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.076 ns) + CELL(0.150 ns) 3.185 ns mult:inst2\|p7\[0\] 2 COMB LCCOMB_X58_Y24_N8 1 " "Info: 2: + IC(2.076 ns) + CELL(0.150 ns) = 3.185 ns; Loc. = LCCOMB_X58_Y24_N8; Fanout = 1; COMB Node = 'mult:inst2\|p7\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.226 ns" { xa[0] mult:inst2|p7[0] } "NODE_NAME" } } { "mult.vhd" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/mult.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 3.269 ns tran8to9:inst\|b\[1\] 3 REG LCFF_X58_Y24_N9 1 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 3.269 ns; Loc. = LCFF_X58_Y24_N9; Fanout = 1; REG Node = 'tran8to9:inst\|b\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { mult:inst2|p7[0] tran8to9:inst|b[1] } "NODE_NAME" } } { "tran8to9.vhd" "" { Text "E:/2008-2008学期工作/第二学期研究生课程/fpga实验课/课程实验报告/课程报告2_加法树8位乘法器/adder/tran8to9.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.193 ns ( 36.49 % ) " "Info: Total cell delay = 1.193 ns ( 36.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.076 ns ( 63.51 % ) " "Info: Total interconnect delay = 2.076 ns ( 63.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.269 ns" { xa[0] mult:inst2|p7[0] tran8to9:inst|b[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.269 ns" { xa[0] xa[0]~combout mult:inst2|p7[0] tran8to9:inst|b[1] } { 0.000ns 0.000ns 2.076ns 0.000ns } { 0.000ns 0.959ns 0.150ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.897 ns" { clk clk~clkctrl tran8to9:inst|b[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.897 ns" { clk clk~combout clk~clkctrl tran8to9:inst|b[1] } { 0.000ns 0.000ns 0.114ns 1.257ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.269 ns" { xa[0] mult:inst2|p7[0] tran8to9:inst|b[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.269 ns" { xa[0] xa[0]~combout mult:inst2|p7[0] tran8to9:inst|b[1] } { 0.000ns 0.000ns 2.076ns 0.000ns } { 0.000ns 0.959ns 0.150ns 0.084ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}