lift.vho

在QuartusII里用VHDL仿真实现电梯控制器

SIGNAL \~GND~1~I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \~GND~1~I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \~GND~1~I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \~GND~1~I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \~GND~1~I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \~GND~1~I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \~GND~1~I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \~GND~1~I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \~GND~1~I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \~GND~1~I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \~GND~1~I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \~VCC~0~I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \~VCC~0~I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \~VCC~0~I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \~VCC~0~I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \~VCC~0~I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \~VCC~0~I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \~VCC~0~I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \~VCC~0~I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \~VCC~0~I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \~VCC~0~I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \~VCC~0~I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \~GND~2~I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \~GND~2~I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \~GND~2~I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \~GND~2~I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \~GND~2~I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \~GND~2~I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \~GND~2~I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \~GND~2~I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \~GND~2~I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \~GND~2~I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \~GND~2~I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \udsig~410sexp3bal_I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \udsig~410sexp3bal_I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \udsig~410sexp3bal_I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \udsig~410sexp3bal_I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \udsig~410sexp3bal_I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \udsig~410sexp3bal_I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \udsig~410sexp3bal_I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \udsig~410sexp3bal_I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \udsig~410sexp3bal_I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \udsig~410sexp3bal_I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \udsig~410sexp3bal_I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \ctrlift~194sexp_I_datain_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \ctrlift~196sexp_I_datain_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \Selector12~275sexp_I_datain_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \ctrlift~198sexp_I_datain_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \ctrlift~200sexp_I_datain_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \clk~dataout\ : std_logic;
SIGNAL \~GND~0\ : std_logic;
SIGNAL \~GND~1\ : std_logic;
SIGNAL \~VCC~0\ : std_logic;
SIGNAL \~GND~2\ : std_logic;
SIGNAL \f1upbutton~dataout\ : std_logic;
SIGNAL \f2dnbutton~dataout\ : std_logic;
SIGNAL \reset~dataout\ : std_logic;
SIGNAL \mylift.state_bit_0~267\ : std_logic;
SIGNAL \stop1button~dataout\ : std_logic;
SIGNAL \stop2button~dataout\ : std_logic;
SIGNAL \stop3button~dataout\ : std_logic;
SIGNAL \stoplight~227\ : std_logic;
SIGNAL \u1|ck2\ : std_logic;
SIGNAL \stoplight[3]~reg0\ : std_logic;
SIGNAL \f3dnbutton~dataout\ : std_logic;
SIGNAL \fdnlight[3]~reg0\ : std_logic;
SIGNAL \stoplight[1]~reg0\ : std_logic;
SIGNAL \mylift.state_bit_0~269\ : std_logic;
SIGNAL \stoplight~218\ : std_logic;
SIGNAL \stoplight[2]~reg0\ : std_logic;
SIGNAL \u1|ck1\ : std_logic;
SIGNAL \mylift.state_bit_0\ : std_logic;
SIGNAL \ctrlift~196sexp\ : std_logic;
SIGNAL \ctrlift~200sexp\ : std_logic;
SIGNAL \mylift.state_bit_1~574\ : std_logic;
SIGNAL \comb~7\ : std_logic;
SIGNAL \comb~9\ : std_logic;
SIGNAL \Selector12~275sexp\ : std_logic;
SIGNAL \ctrlift~198sexp\ : std_logic;
SIGNAL \mylift.state_bit_1~579\ : std_logic;
SIGNAL \ctrlift~194sexp\ : std_logic;
SIGNAL \mylift.state_bit_1\ : std_logic;
SIGNAL \fuplight[1]~reg0\ : std_logic;
SIGNAL \mylift.state_bit_2~92\ : std_logic;
SIGNAL \mylift.state_bit_2~97\ : std_logic;
SIGNAL \mylift.state_bit_2\ : std_logic;
SIGNAL \mylift.state_bit_3~221\ : std_logic;
SIGNAL \mylift.state_bit_3~224\ : std_logic;
SIGNAL \mylift.state_bit_3\ : std_logic;
SIGNAL \Selector13~229\ : std_logic;
SIGNAL cleardn : std_logic;
SIGNAL \fdnlight[2]~reg0\ : std_logic;
SIGNAL \udsig~408\ : std_logic;
SIGNAL \udsig~410sexp3bal\ : std_logic;
SIGNAL udsig : std_logic;
SIGNAL \Selector12~283\ : std_logic;
SIGNAL clearup : std_logic;
SIGNAL \f2upbutton~dataout\ : std_logic;
SIGNAL \fuplight[2]~reg0\ : std_logic;
SIGNAL \udsig~420\ : std_logic;
SIGNAL \doorlight~reg0\ : std_logic;
SIGNAL \u2|segout[0]~6\ : std_logic;
SIGNAL \u2|segout[0]~4\ : std_logic;
SIGNAL \u2|segout\ : std_logic_vector(6 DOWNTO 0);
SIGNAL position : std_logic_vector(1 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs\ : std_logic_vector(15 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs\ : std_logic_vector(22 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|ALT_INV_dffs\ : std_logic_vector(14 DOWNTO 0);
SIGNAL \ALT_INV_fdnlight[3]~reg0\ : std_logic;
SIGNAL \ALT_INV_fdnlight[2]~reg0\ : std_logic;
SIGNAL \ALT_INV_fuplight[2]~reg0\ : std_logic;
SIGNAL \ALT_INV_stoplight[2]~reg0\ : std_logic;
SIGNAL \ALT_INV_stoplight[3]~reg0\ : std_logic;
SIGNAL \u1|cnt1_rtl_0|ALT_INV_dffs\ : std_logic_vector(21 DOWNTO 18);
SIGNAL ALT_INV_udsig : std_logic;
SIGNAL \ALT_INV_comb~7\ : std_logic;
SIGNAL ALT_INV_cleardn : std_logic;
SIGNAL \ALT_INV_comb~9\ : std_logic;
SIGNAL \ALT_INV_stoplight[1]~reg0\ : std_logic;
SIGNAL \ALT_INV_mylift.state_bit_2\ : std_logic;
SIGNAL \ALT_INV_mylift.state_bit_0\ : std_logic;
SIGNAL \ALT_INV_doorlight~reg0\ : std_logic;
SIGNAL \ALT_INV_mylift.state_bit_3\ : std_logic;
SIGNAL ALT_INV_position : std_logic_vector(1 DOWNTO 0);
SIGNAL \ALT_INV_mylift.state_bit_1\ : std_logic;
SIGNAL ALT_INV_clearup : std_logic;
SIGNAL \ALT_INV_fuplight[1]~reg0\ : std_logic;
SIGNAL \ALT_INV_reset~dataout\ : std_logic;
SIGNAL \ALT_INV_f1upbutton~dataout\ : std_logic;
SIGNAL \ALT_INV_f2upbutton~dataout\ : std_logic;
SIGNAL \ALT_INV_f2dnbutton~dataout\ : std_logic;
SIGNAL \ALT_INV_f3dnbutton~dataout\ : std_logic;
SIGNAL \ALT_INV_stop2button~dataout\ : std_logic;
SIGNAL \ALT_INV_stop3button~dataout\ : std_logic;

BEGIN

ww_clk <= clk;
ww_reset <= reset;
ww_f1upbutton <= f1upbutton;
ww_f2upbutton <= f2upbutton;
ww_f2dnbutton <= f2dnbutton;
ww_f3dnbutton <= f3dnbutton;
fuplight <= ww_fuplight;
fdnlight <= ww_fdnlight;
ww_stop1button <= stop1button;
ww_stop2button <= stop2button;
ww_stop3button <= stop3button;
stoplight <= ww_stoplight;
doorlight <= ww_doorlight;
seg <= ww_seg;
upsiglight <= ww_upsiglight;
dnsiglight <= ww_dnsiglight;

\u1|cnt2_rtl_1|dffs[0]~I_pterm0_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd
& gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd);

\u1|cnt2_rtl_1|dffs[0]~I_pterm1_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd
& gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd);

\u1|cnt2_rtl_1|dffs[0]~I_pterm2_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd
& gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd);

\u1|cnt2_rtl_1|dffs[0]~I_pterm3_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd
& gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd);

\u1|cnt2_rtl_1|dffs[0]~I_pterm4_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd
& gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd);

\u1|cnt2_rtl_1|dffs[0]~I_pterm5_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd
& gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd);

\u1|cnt2_rtl_1|dffs[0]~I_pxor_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & 
gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd);

\u1|cnt2_rtl_1|dffs[0]~I_pclk_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & 
gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd);

\u1|cnt2_rtl_1|dffs[0]~I_pena_bus\ <= (vcc & vcc & vcc & vcc & vcc & vcc & vcc & vcc & vcc & vcc & vcc & vcc & vcc & vcc & vcc & vcc & vcc & vcc & vcc & vcc & vcc & vcc & vcc & vcc & vcc & vcc & vcc & vcc & vcc & vcc & vcc & vcc & vcc & vcc & vcc & vcc & 
vcc & vcc & vcc & vcc & vcc & vcc & vcc & vcc & vcc & vcc & vcc & vcc & vcc & vcc & vcc & vcc);

\u1|cnt2_rtl_1|dffs[0]~I_paclr_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd
& gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd);

\u1|cnt2_rtl_1|dffs[0]~I_papre_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd
& gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd);

\u1|cnt2_rtl_1|dffs[1]~I_pterm0_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd
& gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd);

\u1|cnt2_rtl_1|dffs[