lift.vho

来自「在QuartusII里用VHDL仿真实现电梯控制器」· VHO 代码 · 共 967 行 · 第 1/5 页

VHO
967 行
字号
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SIGNAL \u1|cnt2_rtl_1|dffs[11]~I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[11]~I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[11]~I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[11]~I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[11]~I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[11]~I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[11]~I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[11]~I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[11]~I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[11]~I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[12]~I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[12]~I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[12]~I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[12]~I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[12]~I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[12]~I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[12]~I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[12]~I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[12]~I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[12]~I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[12]~I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[13]~I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[13]~I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[13]~I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[13]~I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[13]~I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[13]~I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[13]~I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[13]~I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[13]~I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[13]~I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[13]~I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[14]~I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[14]~I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[14]~I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[14]~I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[14]~I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[14]~I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[14]~I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[14]~I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[14]~I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[14]~I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[14]~I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[15]~I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[15]~I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[15]~I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[15]~I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[15]~I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[15]~I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[15]~I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[15]~I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[15]~I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[15]~I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[15]~I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|ck2~I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|ck2~I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|ck2~I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|ck2~I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|ck2~I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|ck2~I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|ck2~I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|ck2~I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|ck2~I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|ck2~I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|ck2~I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[16]~I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[16]~I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[16]~I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[16]~I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[16]~I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[16]~I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[16]~I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[16]~I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[16]~I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[16]~I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[16]~I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \fdnlight[3]~reg0_I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \fdnlight[3]~reg0_I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \fdnlight[3]~reg0_I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \fdnlight[3]~reg0_I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \fdnlight[3]~reg0_I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \fdnlight[3]~reg0_I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \fdnlight[3]~reg0_I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \fdnlight[3]~reg0_I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \fdnlight[3]~reg0_I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \fdnlight[3]~reg0_I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \fdnlight[3]~reg0_I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \fdnlight[2]~reg0_I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \fdnlight[2]~reg0_I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \fdnlight[2]~reg0_I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \fdnlight[2]~reg0_I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \fdnlight[2]~reg0_I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \fdnlight[2]~reg0_I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \fdnlight[2]~reg0_I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \fdnlight[2]~reg0_I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \fdnlight[2]~reg0_I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \fdnlight[2]~reg0_I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \fdnlight[2]~reg0_I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \fuplight[2]~reg0_I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \fuplight[2]~reg0_I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \fuplight[2]~reg0_I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \fuplight[2]~reg0_I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \fuplight[2]~reg0_I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \fuplight[2]~reg0_I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \fuplight[2]~reg0_I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \fuplight[2]~reg0_I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \fuplight[2]~reg0_I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \fuplight[2]~reg0_I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \fuplight[2]~reg0_I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight~218_I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight~218_I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight~218_I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight~218_I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight~218_I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight~218_I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight~218_I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight~218_I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight~218_I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight~218_I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight~218_I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight[2]~reg0_I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight[2]~reg0_I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight[2]~reg0_I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight[2]~reg0_I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight[2]~reg0_I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight[2]~reg0_I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight[2]~reg0_I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight[2]~reg0_I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight[2]~reg0_I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight[2]~reg0_I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight[2]~reg0_I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight~227_I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight~227_I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight~227_I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight~227_I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight~227_I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight~227_I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight~227_I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight~227_I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight~227_I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight~227_I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight~227_I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight[3]~reg0_I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight[3]~reg0_I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight[3]~reg0_I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight[3]~reg0_I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight[3]~reg0_I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight[3]~reg0_I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight[3]~reg0_I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight[3]~reg0_I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight[3]~reg0_I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight[3]~reg0_I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight[3]~reg0_I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[17]~I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[17]~I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[17]~I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[17]~I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[17]~I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[17]~I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[17]~I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[17]~I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[17]~I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[17]~I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[17]~I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[18]~I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[18]~I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[18]~I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[18]~I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[18]~I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[18]~I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[18]~I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[18]~I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[18]~I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[18]~I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[18]~I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[19]~I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[19]~I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[19]~I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[19]~I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[19]~I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[19]~I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[19]~I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[19]~I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[19]~I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[19]~I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[19]~I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[20]~I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[20]~I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[20]~I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[20]~I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[20]~I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[20]~I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[20]~I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[20]~I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
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lift.vho - 源码说明

本页面展示了「在QuartusII里用VHDL仿真实现电梯控制器」中的 lift.vho 源码文件，采用 VHO 编程语言编写，共 967 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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