lift.vho

来自「在QuartusII里用VHDL仿真实现电梯控制器」· VHO 代码 · 共 967 行 · 第 1/5 页

VHO
967 行
字号
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SIGNAL \u1|cnt1_rtl_0|dffs[20]~I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[20]~I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[20]~I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[21]~I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[21]~I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[21]~I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[21]~I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[21]~I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[21]~I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[21]~I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[21]~I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[21]~I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[21]~I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[21]~I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[22]~I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[22]~I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[22]~I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[22]~I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[22]~I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[22]~I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[22]~I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[22]~I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[22]~I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[22]~I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt1_rtl_0|dffs[22]~I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|ck1~I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|ck1~I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|ck1~I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|ck1~I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|ck1~I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|ck1~I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|ck1~I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|ck1~I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|ck1~I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|ck1~I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|ck1~I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \udsig~408_I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \udsig~408_I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \udsig~408_I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \udsig~408_I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \udsig~408_I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \udsig~408_I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \udsig~408_I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \udsig~408_I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \udsig~408_I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \udsig~408_I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \udsig~408_I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \udsig~I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \udsig~I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \udsig~I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \udsig~I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \udsig~I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \udsig~I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \udsig~I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \udsig~I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \udsig~I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \udsig~I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \udsig~I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \comb~7_I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \comb~7_I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \comb~7_I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \comb~7_I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \comb~7_I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \comb~7_I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \comb~7_I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \comb~7_I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \comb~7_I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \comb~7_I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \comb~7_I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \udsig~420_I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \udsig~420_I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \udsig~420_I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \udsig~420_I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \udsig~420_I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \udsig~420_I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \udsig~420_I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \udsig~420_I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \udsig~420_I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \udsig~420_I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \udsig~420_I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \cleardn~I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \cleardn~I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \cleardn~I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \cleardn~I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \cleardn~I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \cleardn~I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \cleardn~I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \cleardn~I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \cleardn~I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \cleardn~I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \cleardn~I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \comb~9_I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \comb~9_I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \comb~9_I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \comb~9_I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \comb~9_I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \comb~9_I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \comb~9_I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \comb~9_I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \comb~9_I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \comb~9_I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \comb~9_I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight[1]~reg0_I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight[1]~reg0_I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight[1]~reg0_I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight[1]~reg0_I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight[1]~reg0_I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight[1]~reg0_I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight[1]~reg0_I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight[1]~reg0_I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight[1]~reg0_I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight[1]~reg0_I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \stoplight[1]~reg0_I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \mylift.state_bit_2~I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \mylift.state_bit_2~I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \mylift.state_bit_2~I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \mylift.state_bit_2~I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \mylift.state_bit_2~I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \mylift.state_bit_2~I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \mylift.state_bit_2~I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \mylift.state_bit_2~I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \mylift.state_bit_2~I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \mylift.state_bit_2~I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \mylift.state_bit_2~I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \mylift.state_bit_0~I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \mylift.state_bit_0~I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \mylift.state_bit_0~I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \mylift.state_bit_0~I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \mylift.state_bit_0~I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \mylift.state_bit_0~I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \mylift.state_bit_0~I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \mylift.state_bit_0~I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \mylift.state_bit_0~I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \mylift.state_bit_0~I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \mylift.state_bit_0~I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \doorlight~reg0_I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \doorlight~reg0_I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \doorlight~reg0_I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \doorlight~reg0_I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \doorlight~reg0_I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \doorlight~reg0_I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \doorlight~reg0_I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \doorlight~reg0_I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \doorlight~reg0_I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \doorlight~reg0_I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \doorlight~reg0_I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \mylift.state_bit_3~I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \mylift.state_bit_3~I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \mylift.state_bit_3~I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \mylift.state_bit_3~I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \mylift.state_bit_3~I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \mylift.state_bit_3~I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \mylift.state_bit_3~I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \mylift.state_bit_3~I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \mylift.state_bit_3~I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \mylift.state_bit_3~I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \mylift.state_bit_3~I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \position[0]~I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \position[0]~I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \position[0]~I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \position[0]~I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \position[0]~I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \position[0]~I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \position[0]~I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \position[0]~I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \position[0]~I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \position[0]~I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \position[0]~I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u2|segout[2]~I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u2|segout[2]~I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u2|segout[2]~I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u2|segout[2]~I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u2|segout[2]~I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u2|segout[2]~I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u2|segout[2]~I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u2|segout[2]~I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u2|segout[2]~I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u2|segout[2]~I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u2|segout[2]~I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u2|segout[4]~I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u2|segout[4]~I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u2|segout[4]~I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u2|segout[4]~I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u2|segout[4]~I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u2|segout[4]~I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u2|segout[4]~I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u2|segout[4]~I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u2|segout[4]~I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u2|segout[4]~I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u2|segout[4]~I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \position[1]~I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \position[1]~I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \position[1]~I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \position[1]~I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
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lift.vho - 源码说明

本页面展示了「在QuartusII里用VHDL仿真实现电梯控制器」中的 lift.vho 源码文件，采用 VHO 编程语言编写，共 967 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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