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📄 lift.vho

📁 在QuartusII里用VHDL仿真实现电梯控制器
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-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 7.0 Build 33 02/05/2007 SJ Full Version"

-- DATE "07/03/2007 15:39:23"

-- 
-- Device: Altera EPM7128SLC84-6 Package PLCC84
-- 

-- 
-- This VHDL file should be used for ModelSim-Altera (VHDL) only
-- 

LIBRARY IEEE, max;
USE IEEE.std_logic_1164.all;
USE max.max_components.all;

ENTITY 	threelift IS
    PORT (
	clk : IN std_logic;
	reset : IN std_logic;
	f1upbutton : IN std_logic;
	f2upbutton : IN std_logic;
	f2dnbutton : IN std_logic;
	f3dnbutton : IN std_logic;
	fuplight : OUT std_logic_vector(3 DOWNTO 1);
	fdnlight : OUT std_logic_vector(3 DOWNTO 1);
	stop1button : IN std_logic;
	stop2button : IN std_logic;
	stop3button : IN std_logic;
	stoplight : OUT std_logic_vector(3 DOWNTO 1);
	doorlight : OUT std_logic;
	seg : OUT std_logic_vector(6 DOWNTO 0);
	upsiglight : OUT std_logic;
	dnsiglight : OUT std_logic
	);
END threelift;

ARCHITECTURE structure OF threelift IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL ww_clk : std_logic;
SIGNAL ww_reset : std_logic;
SIGNAL ww_f1upbutton : std_logic;
SIGNAL ww_f2upbutton : std_logic;
SIGNAL ww_f2dnbutton : std_logic;
SIGNAL ww_f3dnbutton : std_logic;
SIGNAL ww_fuplight : std_logic_vector(3 DOWNTO 1);
SIGNAL ww_fdnlight : std_logic_vector(3 DOWNTO 1);
SIGNAL ww_stop1button : std_logic;
SIGNAL ww_stop2button : std_logic;
SIGNAL ww_stop3button : std_logic;
SIGNAL ww_stoplight : std_logic_vector(3 DOWNTO 1);
SIGNAL ww_doorlight : std_logic;
SIGNAL ww_seg : std_logic_vector(6 DOWNTO 0);
SIGNAL ww_upsiglight : std_logic;
SIGNAL ww_dnsiglight : std_logic;
SIGNAL \u1|cnt2_rtl_1|dffs[0]~I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[0]~I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[0]~I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[0]~I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[0]~I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[0]~I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[0]~I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[0]~I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[0]~I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[0]~I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[0]~I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[1]~I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[1]~I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[1]~I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[1]~I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[1]~I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[1]~I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[1]~I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[1]~I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[1]~I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[1]~I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[1]~I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[2]~I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[2]~I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[2]~I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[2]~I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[2]~I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[2]~I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[2]~I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[2]~I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[2]~I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[2]~I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[2]~I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[3]~I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[3]~I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[3]~I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[3]~I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[3]~I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[3]~I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[3]~I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[3]~I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[3]~I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[3]~I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[3]~I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[4]~I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[4]~I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[4]~I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[4]~I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[4]~I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[4]~I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[4]~I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[4]~I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[4]~I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[4]~I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[4]~I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[5]~I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[5]~I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[5]~I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[5]~I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[5]~I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[5]~I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[5]~I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[5]~I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[5]~I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[5]~I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[5]~I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[6]~I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[6]~I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[6]~I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[6]~I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[6]~I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[6]~I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[6]~I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[6]~I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[6]~I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[6]~I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[6]~I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[7]~I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[7]~I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[7]~I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[7]~I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[7]~I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[7]~I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[7]~I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[7]~I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[7]~I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[7]~I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[7]~I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[8]~I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[8]~I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[8]~I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[8]~I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[8]~I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[8]~I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[8]~I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[8]~I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[8]~I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[8]~I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[8]~I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[9]~I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[9]~I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[9]~I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[9]~I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[9]~I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[9]~I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[9]~I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[9]~I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[9]~I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[9]~I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[9]~I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[10]~I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[10]~I_pterm1_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[10]~I_pterm2_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[10]~I_pterm3_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[10]~I_pterm4_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[10]~I_pterm5_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[10]~I_pxor_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[10]~I_pclk_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[10]~I_pena_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[10]~I_paclr_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[10]~I_papre_bus\ : std_logic_vector(51 DOWNTO 0);
SIGNAL \u1|cnt2_rtl_1|dffs[11]~I_pterm0_bus\ : std_logic_vector(51 DOWNTO 0);
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