alu.tan.qmsg

设计带进位算术逻辑运算单元

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "sclk " "Info: Assuming node \"sclk\" is an undefined clock" {  } { { "alu.bdf" "" { Schematic "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu.bdf" { { -48 -256 -88 -32 "sclk" "" } } } } { "d:/program files/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus/bin/Assignment Editor.qase" 1 { { 0 "sclk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "bclk " "Info: Assuming node \"bclk\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "alu.bdf" "" { Schematic "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu.bdf" { { 248 -256 -88 264 "bclk" "" } } } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "aclk " "Info: Assuming node \"aclk\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "alu.bdf" "" { Schematic "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu.bdf" { { 96 -256 -88 112 "aclk" "" } } } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "sclk register register lpm_counter1:inst8\|lpm_counter:lpm_counter_component\|cntr_6dh:auto_generated\|safe_q\[1\] lpm_counter1:inst8\|lpm_counter:lpm_counter_component\|cntr_6dh:auto_generated\|safe_q\[3\] 275.03 MHz Internal " "Info: Clock \"sclk\" Internal fmax is restricted to 275.03 MHz between source register \"lpm_counter1:inst8\|lpm_counter:lpm_counter_component\|cntr_6dh:auto_generated\|safe_q\[1\]\" and destination register \"lpm_counter1:inst8\|lpm_counter:lpm_counter_component\|cntr_6dh:auto_generated\|safe_q\[3\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.040 ns + Longest register register " "Info: + Longest register to register delay is 2.040 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter1:inst8\|lpm_counter:lpm_counter_component\|cntr_6dh:auto_generated\|safe_q\[1\] 1 REG LC_X14_Y18_N6 35 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y18_N6; Fanout = 35; REG Node = 'lpm_counter1:inst8\|lpm_counter:lpm_counter_component\|cntr_6dh:auto_generated\|safe_q\[1\]'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[1] } "NODE_NAME" } } { "db/cntr_6dh.tdf" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/db/cntr_6dh.tdf" 66 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.598 ns) + CELL(0.575 ns) 1.173 ns lpm_counter1:inst8\|lpm_counter:lpm_counter_component\|cntr_6dh:auto_generated\|counter_cella1~COUTCOUT1 2 COMB LC_X14_Y18_N6 2 " "Info: 2: + IC(0.598 ns) + CELL(0.575 ns) = 1.173 ns; Loc. = LC_X14_Y18_N6; Fanout = 2; COMB Node = 'lpm_counter1:inst8\|lpm_counter:lpm_counter_component\|cntr_6dh:auto_generated\|counter_cella1~COUTCOUT1'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "1.173 ns" { lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[1] lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|counter_cella1~COUTCOUT1 } "NODE_NAME" } } { "db/cntr_6dh.tdf" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/db/cntr_6dh.tdf" 38 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.253 ns lpm_counter1:inst8\|lpm_counter:lpm_counter_component\|cntr_6dh:auto_generated\|counter_cella2~COUTCOUT1 3 COMB LC_X14_Y18_N7 1 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.253 ns; Loc. = LC_X14_Y18_N7; Fanout = 1; COMB Node = 'lpm_counter1:inst8\|lpm_counter:lpm_counter_component\|cntr_6dh:auto_generated\|counter_cella2~COUTCOUT1'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|counter_cella1~COUTCOUT1 lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|counter_cella2~COUTCOUT1 } "NODE_NAME" } } { "db/cntr_6dh.tdf" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/db/cntr_6dh.tdf" 46 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.787 ns) 2.040 ns lpm_counter1:inst8\|lpm_counter:lpm_counter_component\|cntr_6dh:auto_generated\|safe_q\[3\] 4 REG LC_X14_Y18_N8 25 " "Info: 4: + IC(0.000 ns) + CELL(0.787 ns) = 2.040 ns; Loc. = LC_X14_Y18_N8; Fanout = 25; REG Node = 'lpm_counter1:inst8\|lpm_counter:lpm_counter_component\|cntr_6dh:auto_generated\|safe_q\[3\]'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "0.787 ns" { lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|counter_cella2~COUTCOUT1 lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[3] } "NODE_NAME" } } { "db/cntr_6dh.tdf" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/db/cntr_6dh.tdf" 66 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.442 ns ( 70.69 % ) " "Info: Total cell delay = 1.442 ns ( 70.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.598 ns ( 29.31 % ) " "Info: Total interconnect delay = 0.598 ns ( 29.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "2.040 ns" { lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[1] lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|counter_cella1~COUTCOUT1 lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|counter_cella2~COUTCOUT1 lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[3] } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "2.040 ns" { lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[1] {} lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|counter_cella1~COUTCOUT1 {} lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|counter_cella2~COUTCOUT1 {} lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[3] {} } { 0.000ns 0.598ns 0.000ns 0.000ns } { 0.000ns 0.575ns 0.080ns 0.787ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sclk destination 3.246 ns + Shortest register " "Info: + Shortest clock path from clock \"sclk\" to destination register is 3.246 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns sclk 1 CLK PIN_153 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 4; CLK Node = 'sclk'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { sclk } "NODE_NAME" } } { "alu.bdf" "" { Schematic "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu.bdf" { { -48 -256 -88 -32 "sclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.066 ns) + CELL(0.711 ns) 3.246 ns lpm_counter1:inst8\|lpm_counter:lpm_counter_component\|cntr_6dh:auto_generated\|safe_q\[3\] 2 REG LC_X14_Y18_N8 25 " "Info: 2: + IC(1.066 ns) + CELL(0.711 ns) = 3.246 ns; Loc. = LC_X14_Y18_N8; Fanout = 25; REG Node = 'lpm_counter1:inst8\|lpm_counter:lpm_counter_component\|cntr_6dh:auto_generated\|safe_q\[3\]'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "1.777 ns" { sclk lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[3] } "NODE_NAME" } } { "db/cntr_6dh.tdf" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/db/cntr_6dh.tdf" 66 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.16 % ) " "Info: Total cell delay = 2.180 ns ( 67.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.066 ns ( 32.84 % ) " "Info: Total interconnect delay = 1.066 ns ( 32.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "3.246 ns" { sclk lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[3] } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.246 ns" { sclk {} sclk~out0 {} lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[3] {} } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sclk source 3.246 ns - Longest register " "Info: - Longest clock path from clock \"sclk\" to source register is 3.246 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns sclk 1 CLK PIN_153 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 4; CLK Node = 'sclk'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { sclk } "NODE_NAME" } } { "alu.bdf" "" { Schematic "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu.bdf" { { -48 -256 -88 -32 "sclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.066 ns) + CELL(0.711 ns) 3.246 ns lpm_counter1:inst8\|lpm_counter:lpm_counter_component\|cntr_6dh:auto_generated\|safe_q\[1\] 2 REG LC_X14_Y18_N6 35 " "Info: 2: + IC(1.066 ns) + CELL(0.711 ns) = 3.246 ns; Loc. = LC_X14_Y18_N6; Fanout = 35; REG Node = 'lpm_counter1:inst8\|lpm_counter:lpm_counter_component\|cntr_6dh:auto_generated\|safe_q\[1\]'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "1.777 ns" { sclk lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[1] } "NODE_NAME" } } { "db/cntr_6dh.tdf" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/db/cntr_6dh.tdf" 66 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.16 % ) " "Info: Total cell delay = 2.180 ns ( 67.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.066 ns ( 32.84 % ) " "Info: Total interconnect delay = 1.066 ns ( 32.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "3.246 ns" { sclk lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[1] } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.246 ns" { sclk {} sclk~out0 {} lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[1] {} } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "3.246 ns" { sclk lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[3] } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.246 ns" { sclk {} sclk~out0 {} lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[3] {} } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "3.246 ns" { sclk lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[1] } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.246 ns" { sclk {} sclk~out0 {} lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[1] {} } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "db/cntr_6dh.tdf" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/db/cntr_6dh.tdf" 66 8 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "db/cntr_6dh.tdf" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/db/cntr_6dh.tdf" 66 8 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "2.040 ns" { lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[1] lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|counter_cella1~COUTCOUT1 lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|counter_cella2~COUTCOUT1 lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[3] } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "2.040 ns" { lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[1] {} lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|counter_cella1~COUTCOUT1 {} lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|counter_cella2~COUTCOUT1 {} lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[3] {} } { 0.000ns 0.598ns 0.000ns 0.000ns } { 0.000ns 0.575ns 0.080ns 0.787ns } "" } } { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "3.246 ns" { sclk lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[3] } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.246 ns" { sclk {} sclk~out0 {} lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[3] {} } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "3.246 ns" { sclk lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[1] } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.246 ns" { sclk {} sclk~out0 {} lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[1] {} } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[3] } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[3] {} } {  } {  } "" } } { "db/cntr_6dh.tdf" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/db/cntr_6dh.tdf" 66 8 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "74373b:inst2\|12 IN\[1\] bclk 7.324 ns register " "Info: tsu for register \"74373b:inst2\|12\" (data pin = \"IN\[1\]\", clock pin = \"bclk\") is 7.324 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.843 ns + Longest pin register " "Info: + Longest pin to register delay is 8.843 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns IN\[1\] 1 PIN PIN_79 2 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_79; Fanout = 2; PIN Node = 'IN\[1\]'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { IN[1] } "NODE_NAME" } } { "alu.bdf" "" { Schematic "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu.bdf" { { 80 -256 -88 96 "IN\[8..1\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.778 ns) + CELL(0.590 ns) 8.843 ns 74373b:inst2\|12 2 REG LC_X12_Y19_N9 13 " "Info: 2: + IC(6.778 ns) + CELL(0.590 ns) = 8.843 ns; Loc. = LC_X12_Y19_N9; Fanout = 13; REG Node = '74373b:inst2\|12'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "7.368 ns" { IN[1] 74373b:inst2|12 } "NODE_NAME" } } { "74373b.bdf" "" { Schematic "d:/program files/quartus/libraries/others/maxplus2/74373b.bdf" { { 112 248 312 192 "12" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.065 ns ( 23.35 % ) " "Info: Total cell delay = 2.065 ns ( 23.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.778 ns ( 76.65 % ) " "Info: Total interconnect delay = 6.778 ns ( 76.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "8.843 ns" { IN[1] 74373b:inst2|12 } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "8.843 ns" { IN[1] {} IN[1]~out0 {} 74373b:inst2|12 {} } { 0.000ns 0.000ns 6.778ns } { 0.000ns 1.475ns 0.590ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.864 ns + " "Info: + Micro setup delay of destination is 1.864 ns" {  } { { "74373b.bdf" "" { Schematic "d:/program files/quartus/libraries/others/maxplus2/74373b.bdf" { { 112 248 312 192 "12" "" } } } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "bclk destination 3.383 ns - Shortest register " "Info: - Shortest clock path from clock \"bclk\" to destination register is 3.383 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns bclk 1 CLK PIN_28 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 8; CLK Node = 'bclk'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { bclk } "NODE_NAME" } } { "alu.bdf" "" { Schematic "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu.bdf" { { 248 -256 -88 264 "bclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.622 ns) + CELL(0.292 ns) 3.383 ns 74373b:inst2\|12 2 REG LC_X12_Y19_N9 13 " "Info: 2: + IC(1.622 ns) + CELL(0.292 ns) = 3.383 ns; Loc. = LC_X12_Y19_N9; Fanout = 13; REG Node = '74373b:inst2\|12'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "1.914 ns" { bclk 74373b:inst2|12 } "NODE_NAME" } } { "74373b.bdf" "" { Schematic "d:/program files/quartus/libraries/others/maxplus2/74373b.bdf" { { 112 248 312 192 "12" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.761 ns ( 52.05 % ) " "Info: Total cell delay = 1.761 ns ( 52.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.622 ns ( 47.95 % ) " "Info: Total interconnect delay = 1.622 ns ( 47.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "3.383 ns" { bclk 74373b:inst2|12 } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.383 ns" { bclk {} bclk~out0 {} 74373b:inst2|12 {} } { 0.000ns 0.000ns 1.622ns } { 0.000ns 1.469ns 0.292ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "8.843 ns" { IN[1] 74373b:inst2|12 } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "8.843 ns" { IN[1] {} IN[1]~out0 {} 74373b:inst2|12 {} } { 0.000ns 0.000ns 6.778ns } { 0.000ns 1.475ns 0.590ns } "" } } { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "3.383 ns" { bclk 74373b:inst2|12 } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.383 ns" { bclk {} bclk~out0 {} 74373b:inst2|12 {} } { 0.000ns 0.000ns 1.622ns } { 0.000ns 1.469ns 0.292ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "bclk F\[7\] 74373b:inst2\|14 71.375 ns register " "Info: tco from clock \"bclk\" to destination pin \"F\[7\]\" through register \"74373b:inst2\|14\" is 71.375 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "bclk source 3.195 ns + Longest register " "Info: + Longest clock path from clock \"bclk\" to source register is 3.195 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns bclk 1 CLK PIN_28 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 8; CLK Node = 'bclk'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { bclk } "NODE_NAME" } } { "alu.bdf" "" { Schematic "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu.bdf" { { 248 -256 -88 264 "bclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.612 ns) + CELL(0.114 ns) 3.195 ns 74373b:inst2\|14 2 REG LC_X12_Y17_N2 15 " "Info: 2: + IC(1.612 ns) + CELL(0.114 ns) = 3.195 ns; Loc. = LC_X12_Y17_N2; Fanout = 15; REG Node = '74373b:inst2\|14'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "1.726 ns" { bclk 74373b:inst2|14 } "NODE_NAME" } } { "74373b.bdf" "" { Schematic "d:/program files/quartus/libraries/others/maxplus2/74373b.bdf" { { 288 248 312 368 "14" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.583 ns ( 49.55 % ) " "Info: Total cell delay = 1.583 ns ( 49.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.612 ns ( 50.45 % ) " "Info: Total interconnect delay = 1.612 ns ( 50.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "3.195 ns" { bclk 74373b:inst2|14 } "NODE_NAME" } } { "d:/program files/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus/bin/Technology_Viewer.qrui" "3.195 ns" { bclk {} bclk~out0 {} 74373b:inst2|14 {} } { 0.000ns 0.000ns 1.612ns } { 0.000ns 1.469ns 0.114ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "74373b.bdf" "" { Schematic "d:/program files/quartus/libraries/others/maxplus2/74373b.bdf" { { 288 248 312 368 "14" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "68.180 ns + Longest register pin " "Info: + Longest register to pin delay is 68.180 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns 74373b:inst2\|14 1 REG LC_X12_Y17_N2 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y17_N2; Fanout = 15; REG Node = '74373b:inst2\|14'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { 74373b:inst2|14 } "NODE_NAME" } } { "74373b.bdf" "" { Schematic "d:/program files/quartus/libraries/others/maxplus2/74373b.bdf" { { 288 248 312 368 "14" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.375 ns) + CELL(0.590 ns) 2.965 ns alu181:inst5\|WideOr8~69 2 COMB LC_X11_Y21_N1 1 " "Info: 2: + IC(2.375 ns) + CELL(0.590 ns) = 2.965 ns; Loc. = LC_X11_Y21_N1; Fanout = 1; COMB Node = 'alu181:inst5\|WideOr8~69'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "2.965 ns" { 74373b:inst2|14 alu181:inst5|WideOr8~69 } "NODE_NAME" } } { "alu181.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu181.v" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.436 ns) + CELL(0.590 ns) 3.991 ns alu181:inst5\|WideOr8 3 COMB LC_X11_Y21_N0 11 " "Info: 3: + IC(0.436 ns) + CELL(0.590 ns) = 3.991 ns; Loc. = LC_X11_Y21_N0; Fanout = 11; COMB Node = 'alu181:inst5\|WideOr8'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "1.026 ns" { alu181:inst5|WideOr8~69 alu181:inst5|WideOr8 } "NODE_NAME" } } { "alu181.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu181.v" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.559 ns) + CELL(0.442 ns) 5.992 ns alu181:inst5\|F~73 4 COMB LC_X13_Y20_N9 8 " "Info: 4: + IC(1.559 ns) + CELL(0.442 ns) = 5.992 ns; Loc. = LC_X13_Y20_N9; Fanout = 8; COMB Node = 'alu181:inst5\|F~73'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "2.001 ns" { alu181:inst5|WideOr8 alu181:inst5|F~73 } "NODE_NAME" } } { "alu181.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu181.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.686 ns) + CELL(0.432 ns) 7.110 ns alu181:inst5\|Add11~102COUT1 5 COMB LC_X14_Y20_N0 2 " "Info: 5: + IC(0.686 ns) + CELL(0.432 ns) = 7.110 ns; Loc. = LC_X14_Y20_N0; Fanout = 2; COMB Node = 'alu181:inst5\|Add11~102COUT1'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "1.118 ns" { alu181:inst5|F~73 alu181:inst5|Add11~102COUT1 } "NODE_NAME" } } { "alu181.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu181.v" 108 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 7.190 ns alu181:inst5\|Add11~104COUT1 6 COMB LC_X14_Y20_N1 2 " "Info: 6: + IC(0.000 ns) + CELL(0.080 ns) = 7.190 ns; Loc. = LC_X14_Y20_N1; Fanout = 2; COMB Node = 'alu181:inst5\|Add11~104COUT1'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { alu181:inst5|Add11~102COUT1 alu181:inst5|Add11~104COUT1 } "NODE_NAME" } } { "alu181.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu181.v" 108 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 7.798 ns alu181:inst5\|Add11~105 7 COMB LC_X14_Y20_N2 1 " "Info: 7: + IC(0.000 ns) + CELL(0.608 ns) = 7.798 ns; Loc. = LC_X14_Y20_N2; Fanout = 1; COMB Node = 'alu181:inst5\|Add11~105'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "0.608 ns" { alu181:inst5|Add11~104COUT1 alu181:inst5|Add11~105 } "NODE_NAME" } } { "alu181.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu181.v" 108 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.212 ns) + CELL(0.590 ns) 9.600 ns alu181:inst5\|F~1359 8 COMB LC_X14_Y19_N2 1 " "Info: 8: + IC(1.212 ns) + CELL(0.590 ns) = 9.600 ns; Loc. = LC_X14_Y19_N2; Fanout = 1; COMB Node = 'alu181:inst5\|F~1359'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "1.802 ns" { alu181:inst5|Add11~105 alu181:inst5|F~1359 } "NODE_NAME" } } { "alu181.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu181.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.205 ns) + CELL(0.590 ns) 11.395 ns alu181:inst5\|F~1360 9 COMB LC_X14_Y21_N4 1 " "Info: 9: + IC(1.205 ns) + CELL(0.590 ns) = 11.395 ns; Loc. = LC_X14_Y21_N4; Fanout = 1; COMB Node = 'alu181:inst5\|F~1360'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "1.795 ns" { alu181:inst5|F~1359 alu181:inst5|F~1360 } "NODE_NAME" } } { "alu181.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu181.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.438 ns) + CELL(0.292 ns) 12.125 ns alu181:inst5\|F~1362 10 COMB LC_X14_Y21_N2 1 " "Info: 10: + IC(0.438 ns) + CELL(0.292 ns) = 12.125 ns; Loc. = LC_X14_Y21_N2; Fanout = 1; COMB Node = 'alu181:inst5\|F~1362'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "0.730 ns" { alu181:inst5|F~1360 alu181:inst5|F~1362 } "NODE_NAME" } } { "alu181.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu181.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.422 ns) + CELL(0.590 ns) 13.137 ns alu181:inst5\|Mux7~138 11 COMB LC_X14_Y21_N1 2 " "Info: 11: + IC(0.422 ns) + CELL(0.590 ns) = 13.137 ns; Loc. = LC_X14_Y21_N1; Fanout = 2; COMB Node = 'alu181:inst5\|Mux7~138'" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "1.012 ns" { alu181:inst5|F~1362 alu181:inst5|Mux7~138 } "NODE_NAME" } } { "alu181.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu181.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.673 ns) 14.810 ns alu181:inst5\|Mux7~147 12 COMB LOOP LC_X13_Y21_N4 4 " "Info: 12: + IC(0.000 ns) + CELL(1.673 ns) = 14.810 ns; Loc. = LC_X13_Y21_N4; Fanout = 4; COMB LOOP Node = 'alu181:inst5\|Mux7~147'" { { "Info" "ITDB_PART_OF_SCC" "alu181:inst5\|F~1358 LC_X11_Y17_N9 " "Info: Loc. = LC_X11_Y17_N9; Node \"alu181:inst5\|F~1358\"" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { alu181:inst5|F~1358 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0} { "Info" "ITDB_PART_OF_SCC" "alu181:inst5\|Mux7~147 LC_X13_Y21_N4 " "Info: Loc. = LC_X13_Y21_N4; Node \"alu181:inst5\|Mux7~147\"" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { alu181:inst5|Mux7~147 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0} { "Info" "ITDB_PART_OF_SCC" "alu181:inst5\|Mux7~139 LC_X13_Y21_N5 " "Info: Loc. = LC_X13_Y21_N5; Node \"alu181:inst5\|Mux7~139\"" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { alu181:inst5|Mux7~139 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0} { "Info" "ITDB_PART_OF_SCC" "alu181:inst5\|Add2~59 LC_X11_Y17_N0 " "Info: Loc. = LC_X11_Y17_N0; Node \"alu181:inst5\|Add2~59\"" {  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { alu181:inst5|Add2~59 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0}  } { { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { alu181:inst5|F~1358 } "NODE_NAME" } } { "alu181.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu181.v" 6 -1 0 } } { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { alu181:inst5|Mux7~147 } "NODE_NAME" } } { "alu181.v" "" { Text "D:/Documents and Settings/WANG YE/My Documents/计算机组成原理/实验二/alu/alu181.v" 11 -1 0 } } { "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/bin/TimingClosureFloorplan.fld" "" "" { alu181:inst5|Mux7~139 } "NODE_NAME" } } { "alu181.v" "" { Text "D:/Documents and Settings/WANG YE/My Docume