alu.sim.rpt

来自「设计带进位算术逻辑运算单元」· RPT 代码 · 共 369 行 · 第 1/5 页

; Group bus channels in simulation results                                                   ; Off        ; Off           ;
; Preserve fewer signal transitions to reduce memory requirements                            ; On         ; On            ;
; Trigger vector comparison with the specified mode                                          ; INPUT_EDGE ; INPUT_EDGE    ;
; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off        ; Off           ;
; Overwrite Waveform Inputs With Simulation Outputs                                          ; Off        ;               ;
; Perform Glitch Filtering in Timing Simulation                                              ; Auto       ; Auto          ;
+--------------------------------------------------------------------------------------------+------------+---------------+


+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.


+--------------------------------------------------------------------+
; Coverage Summary                                                   ;
+-----------------------------------------------------+--------------+
; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;      42.49 % ;
; Total nodes checked                                 ; 1342         ;
; Total output ports checked                          ; 1398         ;
; Total output ports with complete 1/0-value coverage ; 594          ;
; Total output ports with no 1/0-value coverage       ; 166          ;
; Total output ports with no 1-value coverage         ; 539          ;
; Total output ports with no 0-value coverage         ; 431          ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                                                                                                 ;
+--------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                        ; Output Port Name                                                                                      ; Output Port Type ;
+--------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------+------------------+
; |alu|aclk                                                                                        ; |alu|aclk                                                                                             ; out              ;
; |alu|IN[8]                                                                                       ; |alu|IN[8]                                                                                            ; out              ;
; |alu|IN[7]                                                                                       ; |alu|IN[7]                                                                                            ; out              ;
; |alu|IN[6]                                                                                       ; |alu|IN[6]                                                                                            ; out              ;
; |alu|IN[5]                                                                                       ; |alu|IN[5]                                                                                            ; out              ;
; |alu|IN[3]                                                                                       ; |alu|IN[3]                                                                                            ; out              ;
; |alu|IN[1]                                                                                       ; |alu|IN[1]                                                                                            ; out              ;
; |alu|bclk                                                                                        ; |alu|bclk                                                                                             ; out              ;
; |alu|sclk                                                                                        ; |alu|sclk                                                                                             ; out              ;
; |alu|F[7]                                                                                        ; |alu|F[7]                                                                                             ; pin_out          ;
; |alu|F[6]                                                                                        ; |alu|F[6]                                                                                             ; pin_out          ;
; |alu|F[5]                                                                                        ; |alu|F[5]                                                                                             ; pin_out          ;
; |alu|F[4]                                                                                        ; |alu|F[4]                                                                                             ; pin_out          ;
; |alu|F[3]                                                                                        ; |alu|F[3]                                                                                             ; pin_out          ;
; |alu|F[2]                                                                                        ; |alu|F[2]                                                                                             ; pin_out          ;
; |alu|F[1]                                                                                        ; |alu|F[1]                                                                                             ; pin_out          ;
; |alu|F[0]                                                                                        ; |alu|F[0]                                                                                             ; pin_out          ;
; |alu|S[3]                                                                                        ; |alu|S[3]                                                                                             ; pin_out          ;
; |alu|S[2]                                                                                        ; |alu|S[2]                                                                                             ; pin_out          ;
; |alu|S[1]                                                                                        ; |alu|S[1]                                                                                             ; pin_out          ;
; |alu|S[0]                                                                                        ; |alu|S[0]                                                                                             ; pin_out          ;
; |alu|lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|counter_cella0 ; |alu|lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[0]           ; regout           ;
; |alu|lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|counter_cella0 ; |alu|lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|counter_cella0~COUT ; cout             ;
; |alu|lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|counter_cella1 ; |alu|lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[1]           ; regout           ;
; |alu|lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|counter_cella1 ; |alu|lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|counter_cella1~COUT ; cout             ;
; |alu|lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|counter_cella2 ; |alu|lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[2]           ; regout           ;
; |alu|lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|counter_cella2 ; |alu|lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|counter_cella2~COUT ; cout             ;
; |alu|lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|counter_cella3 ; |alu|lpm_counter1:inst8|lpm_counter:lpm_counter_component|cntr_6dh:auto_generated|safe_q[3]           ; regout           ;
; |alu|alu181:inst5|F~8                                                                            ; |alu|alu181:inst5|F~8                                                                                 ; out              ;
; |alu|alu181:inst5|F~10                                                                           ; |alu|alu181:inst5|F~10                                                                                ; out              ;
; |alu|alu181:inst5|F~14                                                                           ; |alu|alu181:inst5|F~14                                                                                ; out              ;
; |alu|alu181:inst5|F~15                                                                           ; |alu|alu181:inst5|F~15                                                                                ; out              ;
; |alu|alu181:inst5|F~19                                                                           ; |alu|alu181:inst5|F~19                                                                                ; out              ;
; |alu|alu181:inst5|F~30                                                                           ; |alu|alu181:inst5|F~30                                                                                ; out              ;
; |alu|alu181:inst5|F~31                                                                           ; |alu|alu181:inst5|F~31                                                                                ; out              ;
; |alu|alu181:inst5|F~32                                                                           ; |alu|alu181:inst5|F~32                                                                                ; out              ;
; |alu|alu181:inst5|F~33                                                                           ; |alu|alu181:inst5|F~33                                                                                ; out              ;