prev_cmp_exercise_5_3_4_3.tan.qmsg

CLK 为其时钟脉冲 M 控制工作模式 CO 为允许带进位移位输入 S 控制移位模式0-3 D[7..0]是移位数据输入 QB[7..0]是移位数据输出 CN是移位数

{ "Info" "ITDB_FULL_TPD_RESULT" "A\[3\] F\[20\] 43.028 ns Longest " "Info: Longest tpd from source pin \"A\[3\]\" to destination pin \"F\[20\]\" is 43.028 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns A\[3\] 1 PIN PIN_38 44 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_38; Fanout = 44; PIN Node = 'A\[3\]'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { A[3] } "NODE_NAME" } } { "EXERCISE_5_3_4_3.bdf" "" { Schematic "D:/DOCUMENTS/DigitalLogicCircuit/PrinciplesOfComputerComposition/EXERCISE_5_3_4_3/EXERCISE_5_3_4_3.bdf" { { 40 0 168 56 "A\[7..0\]" "" } { 184 0 168 200 "A\[15..8\]" "" } { 328 0 168 344 "A\[23..16\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(8.482 ns) + CELL(0.292 ns) 10.243 ns ALU:inst\|MEDI~497 2 COMB LC_X21_Y16_N9 6 " "Info: 2: + IC(8.482 ns) + CELL(0.292 ns) = 10.243 ns; Loc. = LC_X21_Y16_N9; Fanout = 6; COMB Node = 'ALU:inst\|MEDI~497'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "8.774 ns" { A[3] ALU:inst|MEDI~497 } "NODE_NAME" } } { "ALU.v" "" { Text "D:/DOCUMENTS/DigitalLogicCircuit/PrinciplesOfComputerComposition/EXERCISE_5_3_4_3/ALU.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.941 ns) + CELL(0.423 ns) 12.607 ns ALU:inst\|Add2~53 3 COMB LC_X14_Y18_N3 2 " "Info: 3: + IC(1.941 ns) + CELL(0.423 ns) = 12.607 ns; Loc. = LC_X14_Y18_N3; Fanout = 2; COMB Node = 'ALU:inst\|Add2~53'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.364 ns" { ALU:inst|MEDI~497 ALU:inst|Add2~53 } "NODE_NAME" } } { "ALU.v" "" { Text "D:/DOCUMENTS/DigitalLogicCircuit/PrinciplesOfComputerComposition/EXERCISE_5_3_4_3/ALU.v" 60 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 12.785 ns ALU:inst\|Add2~51 4 COMB LC_X14_Y18_N4 4 " "Info: 4: + IC(0.000 ns) + CELL(0.178 ns) = 12.785 ns; Loc. = LC_X14_Y18_N4; Fanout = 4; COMB Node = 'ALU:inst\|Add2~51'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.178 ns" { ALU:inst|Add2~53 ALU:inst|Add2~51 } "NODE_NAME" } } { "ALU.v" "" { Text "D:/DOCUMENTS/DigitalLogicCircuit/PrinciplesOfComputerComposition/EXERCISE_5_3_4_3/ALU.v" 60 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.621 ns) 13.406 ns ALU:inst\|Add2~48 5 COMB LC_X14_Y18_N5 4 " "Info: 5: + IC(0.000 ns) + CELL(0.621 ns) = 13.406 ns; Loc. = LC_X14_Y18_N5; Fanout = 4; COMB Node = 'ALU:inst\|Add2~48'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.621 ns" { ALU:inst|Add2~51 ALU:inst|Add2~48 } "NODE_NAME" } } { "ALU.v" "" { Text "D:/DOCUMENTS/DigitalLogicCircuit/PrinciplesOfComputerComposition/EXERCISE_5_3_4_3/ALU.v" 60 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.256 ns) + CELL(0.575 ns) 15.237 ns ALU:inst\|Add3~49COUT1 6 COMB LC_X14_Y17_N5 2 " "Info: 6: + IC(1.256 ns) + CELL(0.575 ns) = 15.237 ns; Loc. = LC_X14_Y17_N5; Fanout = 2; COMB Node = 'ALU:inst\|Add3~49COUT1'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.831 ns" { ALU:inst|Add2~48 ALU:inst|Add3~49COUT1 } "NODE_NAME" } } { "ALU.v" "" { Text "D:/DOCUMENTS/DigitalLogicCircuit/PrinciplesOfComputerComposition/EXERCISE_5_3_4_3/ALU.v" 60 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 15.317 ns ALU:inst\|Add3~47COUT1 7 COMB LC_X14_Y17_N6 2 " "Info: 7: + IC(0.000 ns) + CELL(0.080 ns) = 15.317 ns; Loc. = LC_X14_Y17_N6; Fanout = 2; COMB Node = 'ALU:inst\|Add3~47COUT1'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { ALU:inst|Add3~49COUT1 ALU:inst|Add3~47COUT1 } "NODE_NAME" } } { "ALU.v" "" { Text "D:/DOCUMENTS/DigitalLogicCircuit/PrinciplesOfComputerComposition/EXERCISE_5_3_4_3/ALU.v" 60 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 15.397 ns ALU:inst\|Add3~45COUT1 8 COMB LC_X14_Y17_N7 1 " "Info: 8: + IC(0.000 ns) + CELL(0.080 ns) = 15.397 ns; Loc. = LC_X14_Y17_N7; Fanout = 1; COMB Node = 'ALU:inst\|Add3~45COUT1'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { ALU:inst|Add3~47COUT1 ALU:inst|Add3~45COUT1 } "NODE_NAME" } } { "ALU.v" "" { Text "D:/DOCUMENTS/DigitalLogicCircuit/PrinciplesOfComputerComposition/EXERCISE_5_3_4_3/ALU.v" 60 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 16.005 ns ALU:inst\|Add3~42 9 COMB LC_X14_Y17_N8 1 " "Info: 9: + IC(0.000 ns) + CELL(0.608 ns) = 16.005 ns; Loc. = LC_X14_Y17_N8; Fanout = 1; COMB Node = 'ALU:inst\|Add3~42'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.608 ns" { ALU:inst|Add3~45COUT1 ALU:inst|Add3~42 } "NODE_NAME" } } { "ALU.v" "" { Text "D:/DOCUMENTS/DigitalLogicCircuit/PrinciplesOfComputerComposition/EXERCISE_5_3_4_3/ALU.v" 60 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.296 ns) + CELL(0.114 ns) 18.415 ns ALU:inst\|Mux17~633 10 COMB LC_X26_Y16_N3 1 " "Info: 10: + IC(2.296 ns) + CELL(0.114 ns) = 18.415 ns; Loc. = LC_X26_Y16_N3; Fanout = 1; COMB Node = 'ALU:inst\|Mux17~633'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.410 ns" { ALU:inst|Add3~42 ALU:inst|Mux17~633 } "NODE_NAME" } } { "ALU.v" "" { Text "D:/DOCUMENTS/DigitalLogicCircuit/PrinciplesOfComputerComposition/EXERCISE_5_3_4_3/ALU.v" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.786 ns) + CELL(0.292 ns) 21.493 ns ALU:inst\|Mux17~634 11 COMB LC_X15_Y11_N7 1 " "Info: 11: + IC(2.786 ns) + CELL(0.292 ns) = 21.493 ns; Loc. = LC_X15_Y11_N7; Fanout = 1; COMB Node = 'ALU:inst\|Mux17~634'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.078 ns" { ALU:inst|Mux17~633 ALU:inst|Mux17~634 } "NODE_NAME" } } { "ALU.v" "" { Text "D:/DOCUMENTS/DigitalLogicCircuit/PrinciplesOfComputerComposition/EXERCISE_5_3_4_3/ALU.v" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.453 ns) + CELL(0.292 ns) 22.238 ns ALU:inst\|Mux17~636 12 COMB LC_X15_Y11_N8 1 " "Info: 12: + IC(0.453 ns) + CELL(0.292 ns) = 22.238 ns; Loc. = LC_X15_Y11_N8; Fanout = 1; COMB Node = 'ALU:inst\|Mux17~636'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.745 ns" { ALU:inst|Mux17~634 ALU:inst|Mux17~636 } "NODE_NAME" } } { "ALU.v" "" { Text "D:/DOCUMENTS/DigitalLogicCircuit/PrinciplesOfComputerComposition/EXERCISE_5_3_4_3/ALU.v" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.444 ns) + CELL(0.292 ns) 22.974 ns ALU:inst\|MEDI\[8\]~473 13 COMB LC_X15_Y11_N4 2 " "Info: 13: + IC(0.444 ns) + CELL(0.292 ns) = 22.974 ns; Loc. = LC_X15_Y11_N4; Fanout = 2; COMB Node = 'ALU:inst\|MEDI\[8\]~473'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.736 ns" { ALU:inst|Mux17~636 ALU:inst|MEDI[8]~473 } "NODE_NAME" } } { "ALU.v" "" { Text "D:/DOCUMENTS/DigitalLogicCircuit/PrinciplesOfComputerComposition/EXERCISE_5_3_4_3/ALU.v" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.444 ns) + CELL(0.114 ns) 25.532 ns ALU:inst\|MEDI\[8\]~474 14 COMB LC_X22_Y17_N6 5 " "Info: 14: + IC(2.444 ns) + CELL(0.114 ns) = 25.532 ns; Loc. = LC_X22_Y17_N6; Fanout = 5; COMB Node = 'ALU:inst\|MEDI\[8\]~474'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.558 ns" { ALU:inst|MEDI[8]~473 ALU:inst|MEDI[8]~474 } "NODE_NAME" } } { "ALU.v" "" { Text "D:/DOCUMENTS/DigitalLogicCircuit/PrinciplesOfComputerComposition/EXERCISE_5_3_4_3/ALU.v" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.230 ns) + CELL(0.114 ns) 26.876 ns ALU:inst1\|MEDI\[8\]~627 15 COMB LC_X24_Y17_N5 5 " "Info: 15: + IC(1.230 ns) + CELL(0.114 ns) = 26.876 ns; Loc. = LC_X24_Y17_N5; Fanout = 5; COMB Node = 'ALU:inst1\|MEDI\[8\]~627'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.344 ns" { ALU:inst|MEDI[8]~474 ALU:inst1|MEDI[8]~627 } "NODE_NAME" } } { "ALU.v" "" { Text "D:/DOCUMENTS/DigitalLogicCircuit/PrinciplesOfComputerComposition/EXERCISE_5_3_4_3/ALU.v" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.431 ns) + CELL(0.114 ns) 27.421 ns ALU:inst1\|CO~107 16 COMB LC_X24_Y17_N4 7 " "Info: 16: + IC(0.431 ns) + CELL(0.114 ns) = 27.421 ns; Loc. = LC_X24_Y17_N4; Fanout = 7; COMB Node = 'ALU:inst1\|CO~107'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.545 ns" { ALU:inst1|MEDI[8]~627 ALU:inst1|CO~107 } "NODE_NAME" } } { "ALU.v" "" { Text "D:/DOCUMENTS/DigitalLogicCircuit/PrinciplesOfComputerComposition/EXERCISE_5_3_4_3/ALU.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.597 ns) + CELL(0.114 ns) 29.132 ns ALU:inst2\|F\[1\]~3734 17 COMB LC_X27_Y18_N6 7 " "Info: 17: + IC(1.597 ns) + CELL(0.114 ns) = 29.132 ns; Loc. = LC_X27_Y18_N6; Fanout = 7; COMB Node = 'ALU:inst2\|F\[1\]~3734'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.711 ns" { ALU:inst1|CO~107 ALU:inst2|F[1]~3734 } "NODE_NAME" } } { "ALU.v" "" { Text "D:/DOCUMENTS/DigitalLogicCircuit/PrinciplesOfComputerComposition/EXERCISE_5_3_4_3/ALU.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.173 ns) + CELL(0.442 ns) 30.747 ns ALU:inst2\|F\[4\]~3783 18 COMB LC_X29_Y18_N0 1 " "Info: 18: + IC(1.173 ns) + CELL(0.442 ns) = 30.747 ns; Loc. = LC_X29_Y18_N0; Fanout = 1; COMB Node = 'ALU:inst2\|F\[4\]~3783'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.615 ns" { ALU:inst2|F[1]~3734 ALU:inst2|F[4]~3783 } "NODE_NAME" } } { "ALU.v" "" { Text "D:/DOCUMENTS/DigitalLogicCircuit/PrinciplesOfComputerComposition/EXERCISE_5_3_4_3/ALU.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.261 ns) + CELL(0.590 ns) 32.598 ns ALU:inst2\|F\[4\]~3784 19 COMB LC_X29_Y20_N6 1 " "Info: 19: + IC(1.261 ns) + CELL(0.590 ns) = 32.598 ns; Loc. = LC_X29_Y20_N6; Fanout = 1; COMB Node = 'ALU:inst2\|F\[4\]~3784'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.851 ns" { ALU:inst2|F[4]~3783 ALU:inst2|F[4]~3784 } "NODE_NAME" } } { "ALU.v" "" { Text "D:/DOCUMENTS/DigitalLogicCircuit/PrinciplesOfComputerComposition/EXERCISE_5_3_4_3/ALU.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.692 ns) + CELL(0.442 ns) 33.732 ns ALU:inst2\|F\[4\]~3785 20 COMB LC_X29_Y20_N2 1 " "Info: 20: + IC(0.692 ns) + CELL(0.442 ns) = 33.732 ns; Loc. = LC_X29_Y20_N2; Fanout = 1; COMB Node = 'ALU:inst2\|F\[4\]~3785'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.134 ns" { ALU:inst2|F[4]~3784 ALU:inst2|F[4]~3785 } "NODE_NAME" } } { "ALU.v" "" { Text "D:/DOCUMENTS/DigitalLogicCircuit/PrinciplesOfComputerComposition/EXERCISE_5_3_4_3/ALU.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.084 ns) + CELL(0.442 ns) 35.258 ns ALU:inst2\|F\[4\]~3786 21 COMB LC_X31_Y20_N6 1 " "Info: 21: + IC(1.084 ns) + CELL(0.442 ns) = 35.258 ns; Loc. = LC_X31_Y20_N6; Fanout = 1; COMB Node = 'ALU:inst2\|F\[4\]~3786'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.526 ns" { ALU:inst2|F[4]~3785 ALU:inst2|F[4]~3786 } "NODE_NAME" } } { "ALU.v" "" { Text "D:/DOCUMENTS/DigitalLogicCircuit/PrinciplesOfComputerComposition/EXERCISE_5_3_4_3/ALU.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.423 ns) + CELL(0.114 ns) 35.795 ns ALU:inst2\|F\[4\]~3787 22 COMB LC_X31_Y20_N8 1 " "Info: 22: + IC(0.423 ns) + CELL(0.114 ns) = 35.795 ns; Loc. = LC_X31_Y20_N8; Fanout = 1; COMB Node = 'ALU:inst2\|F\[4\]~3787'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.537 ns" { ALU:inst2|F[4]~3786 ALU:inst2|F[4]~3787 } "NODE_NAME" } } { "ALU.v" "" { Text "D:/DOCUMENTS/DigitalLogicCircuit/PrinciplesOfComputerComposition/EXERCISE_5_3_4_3/ALU.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.221 ns) + CELL(0.114 ns) 37.130 ns ALU:inst2\|F\[4\]~3788 23 COMB LC_X31_Y18_N3 1 " "Info: 23: + IC(1.221 ns) + CELL(0.114 ns) = 37.130 ns; Loc. = LC_X31_Y18_N3; Fanout = 1; COMB Node = 'ALU:inst2\|F\[4\]~3788'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.335 ns" { ALU:inst2|F[4]~3787 ALU:inst2|F[4]~3788 } "NODE_NAME" } } { "ALU.v" "" { Text "D:/DOCUMENTS/DigitalLogicCircuit/PrinciplesOfComputerComposition/EXERCISE_5_3_4_3/ALU.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 37.426 ns ALU:inst2\|F\[4\]~3789 24 COMB LC_X31_Y18_N4 1 " "Info: 24: + IC(0.182 ns) + CELL(0.114 ns) = 37.426 ns; Loc. = LC_X31_Y18_N4; Fanout = 1; COMB Node = 'ALU:inst2\|F\[4\]~3789'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.296 ns" { ALU:inst2|F[4]~3788 ALU:inst2|F[4]~3789 } "NODE_NAME" } } { "ALU.v" "" { Text "D:/DOCUMENTS/DigitalLogicCircuit/PrinciplesOfComputerComposition/EXERCISE_5_3_4_3/ALU.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.478 ns) + CELL(2.124 ns) 43.028 ns F\[20\] 25 PIN PIN_158 0 " "Info: 25: + IC(3.478 ns) + CELL(2.124 ns) = 43.028 ns; Loc. = PIN_158; Fanout = 0; PIN Node = 'F\[20\]'" {  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.602 ns" { ALU:inst2|F[4]~3789 F[20] } "NODE_NAME" } } { "EXERCISE_5_3_4_3.bdf" "" { Schematic "D:/DOCUMENTS/DigitalLogicCircuit/PrinciplesOfComputerComposition/EXERCISE_5_3_4_3/EXERCISE_5_3_4_3.bdf" { { 40 528 704 56 "F\[7..0\]" "" } { 184 528 704 200 "F\[15..8\]" "" } { 328 528 704 344 "F\[23..16\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.154 ns ( 23.60 % ) " "Info: Total cell delay = 10.154 ns ( 23.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "32.874 ns ( 76.40 % ) " "Info: Total interconnect delay = 32.874 ns ( 76.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "43.028 ns" { A[3] ALU:inst|MEDI~497 ALU:inst|Add2~53 ALU:inst|Add2~51 ALU:inst|Add2~48 ALU:inst|Add3~49COUT1 ALU:inst|Add3~47COUT1 ALU:inst|Add3~45COUT1 ALU:inst|Add3~42 ALU:inst|Mux17~633 ALU:inst|Mux17~634 ALU:inst|Mux17~636 ALU:inst|MEDI[8]~473 ALU:inst|MEDI[8]~474 ALU:inst1|MEDI[8]~627 ALU:inst1|CO~107 ALU:inst2|F[1]~3734 ALU:inst2|F[4]~3783 ALU:inst2|F[4]~3784 ALU:inst2|F[4]~3785 ALU:inst2|F[4]~3786 ALU:inst2|F[4]~3787 ALU:inst2|F[4]~3788 ALU:inst2|F[4]~3789 F[20] } "NODE_NAME" } } { "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/program files/altera/quartus/bin/Technology_Viewer.qrui" "43.028 ns" { A[3] {} A[3]~out0 {} ALU:inst|MEDI~497 {} ALU:inst|Add2~53 {} ALU:inst|Add2~51 {} ALU:inst|Add2~48 {} ALU:inst|Add3~49COUT1 {} ALU:inst|Add3~47COUT1 {} ALU:inst|Add3~45COUT1 {} ALU:inst|Add3~42 {} ALU:inst|Mux17~633 {} ALU:inst|Mux17~634 {} ALU:inst|Mux17~636 {} ALU:inst|MEDI[8]~473 {} ALU:inst|MEDI[8]~474 {} ALU:inst1|MEDI[8]~627 {} ALU:inst1|CO~107 {} ALU:inst2|F[1]~3734 {} ALU:inst2|F[4]~3783 {} ALU:inst2|F[4]~3784 {} ALU:inst2|F[4]~3785 {} ALU:inst2|F[4]~3786 {} ALU:inst2|F[4]~3787 {} ALU:inst2|F[4]~3788 {} ALU:inst2|F[4]~3789 {} F[20] {} } { 0.000ns 0.000ns 8.482ns 1.941ns 0.000ns 0.000ns 1.256ns 0.000ns 0.000ns 0.000ns 2.296ns 2.786ns 0.453ns 0.444ns 2.444ns 1.230ns 0.431ns 1.597ns 1.173ns 1.261ns 0.692ns 1.084ns 0.423ns 1.221ns 0.182ns 3.478ns } { 0.000ns 1.469ns 0.292ns 0.423ns 0.178ns 0.621ns 0.575ns 0.080ns 0.080ns 0.608ns 0.114ns 0.292ns 0.292ns 0.292ns 0.114ns 0.114ns 0.114ns 0.114ns 0.442ns 0.590ns 0.442ns 0.442ns 0.114ns 0.114ns 0.114ns 2.124ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "114 " "Info: Allocated 114 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 25 16:11:37 2009 " "Info: Processing ended: Sat Apr 25 16:11:37 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}