exercise_5_3_4_3.map.qmsg

CLK 为其时钟脉冲 M 控制工作模式 CO 为允许带进位移位输入 S 控制移位模式0-3 D[7..0]是移位数据输入 QB[7..0]是移位数据输出 CN是移位数

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 25 16:11:49 2009 " "Info: Processing started: Sat Apr 25 16:11:49 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off EXERCISE_5_3_4_3 -c EXERCISE_5_3_4_3 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off EXERCISE_5_3_4_3 -c EXERCISE_5_3_4_3" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ALU.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ALU.v" { { "Info" "ISGN_ENTITY_NAME" "1 ALU " "Info: Found entity 1: ALU" {  } { { "ALU.v" "" { Text "D:/DOCUMENTS/DigitalLogicCircuit/PrinciplesOfComputerComposition/EXERCISE_5_3_4_3/ALU.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "EXERCISE_5_3_4_3.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file EXERCISE_5_3_4_3.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 EXERCISE_5_3_4_3 " "Info: Found entity 1: EXERCISE_5_3_4_3" {  } { { "EXERCISE_5_3_4_3.bdf" "" { Schematic "D:/DOCUMENTS/DigitalLogicCircuit/PrinciplesOfComputerComposition/EXERCISE_5_3_4_3/EXERCISE_5_3_4_3.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "EXERCISE_5_3_4_3 " "Info: Elaborating entity \"EXERCISE_5_3_4_3\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ALU ALU:inst2 " "Info: Elaborating entity \"ALU\" for hierarchy \"ALU:inst2\"" {  } { { "EXERCISE_5_3_4_3.bdf" "inst2" { Schematic "D:/DOCUMENTS/DigitalLogicCircuit/PrinciplesOfComputerComposition/EXERCISE_5_3_4_3/EXERCISE_5_3_4_3.bdf" { { 304 320 440 432 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "MEDI ALU.v(12) " "Warning (10240): Verilog HDL Always Construct warning at ALU.v(12): inferring latch(es) for variable \"MEDI\", which holds its previous value in one or more paths through the always construct" {  } { { "ALU.v" "" { Text "D:/DOCUMENTS/DigitalLogicCircuit/PrinciplesOfComputerComposition/EXERCISE_5_3_4_3/ALU.v" 12 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "MEDI\[0\] ALU.v(35) " "Info (10041): Inferred latch for \"MEDI\[0\]\" at ALU.v(35)" {  } { { "ALU.v" "" { Text "D:/DOCUMENTS/DigitalLogicCircuit/PrinciplesOfComputerComposition/EXERCISE_5_3_4_3/ALU.v" 35 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "MEDI\[1\] ALU.v(35) " "Info (10041): Inferred latch for \"MEDI\[1\]\" at ALU.v(35)" {  } { { "ALU.v" "" { Text "D:/DOCUMENTS/DigitalLogicCircuit/PrinciplesOfComputerComposition/EXERCISE_5_3_4_3/ALU.v" 35 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "MEDI\[2\] ALU.v(35) " "Info (10041): Inferred latch for \"MEDI\[2\]\" at ALU.v(35)" {  } { { "ALU.v" "" { Text "D:/DOCUMENTS/DigitalLogicCircuit/PrinciplesOfComputerComposition/EXERCISE_5_3_4_3/ALU.v" 35 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "MEDI\[3\] ALU.v(35) " "Info (10041): Inferred latch for \"MEDI\[3\]\" at ALU.v(35)" {  } { { "ALU.v" "" { Text "D:/DOCUMENTS/DigitalLogicCircuit/PrinciplesOfComputerComposition/EXERCISE_5_3_4_3/ALU.v" 35 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "MEDI\[4\] ALU.v(35) " "Info (10041): Inferred latch for \"MEDI\[4\]\" at ALU.v(35)" {  } { { "ALU.v" "" { Text "D:/DOCUMENTS/DigitalLogicCircuit/PrinciplesOfComputerComposition/EXERCISE_5_3_4_3/ALU.v" 35 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "MEDI\[5\] ALU.v(35) " "Info (10041): Inferred latch for \"MEDI\[5\]\" at ALU.v(35)" {  } { { "ALU.v" "" { Text "D:/DOCUMENTS/DigitalLogicCircuit/PrinciplesOfComputerComposition/EXERCISE_5_3_4_3/ALU.v" 35 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "MEDI\[6\] ALU.v(35) " "Info (10041): Inferred latch for \"MEDI\[6\]\" at ALU.v(35)" {  } { { "ALU.v" "" { Text "D:/DOCUMENTS/DigitalLogicCircuit/PrinciplesOfComputerComposition/EXERCISE_5_3_4_3/ALU.v" 35 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "MEDI\[7\] ALU.v(35) " "Info (10041): Inferred latch for \"MEDI\[7\]\" at ALU.v(35)" {  } { { "ALU.v" "" { Text "D:/DOCUMENTS/DigitalLogicCircuit/PrinciplesOfComputerComposition/EXERCISE_5_3_4_3/ALU.v" 35 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "MEDI\[8\] ALU.v(35) " "Info (10041): Inferred latch for \"MEDI\[8\]\" at ALU.v(35)" {  } { { "ALU.v" "" { Text "D:/DOCUMENTS/DigitalLogicCircuit/PrinciplesOfComputerComposition/EXERCISE_5_3_4_3/ALU.v" 35 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "1337 " "Info: Implemented 1337 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "54 " "Info: Implemented 54 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "25 " "Info: Implemented 25 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "1258 " "Info: Implemented 1258 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "137 " "Info: Allocated 137 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 25 16:12:03 2009 " "Info: Processing ended: Sat Apr 25 16:12:03 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Info: Elapsed time: 00:00:14" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}