exercise_5_3_4_3.hif

CLK 为其时钟脉冲 M 控制工作模式 CO 为允许带进位移位输入 S 控制移位模式0-3 D[7..0]是移位数据输入 QB[7..0]是移位数据输出 CN是移位数

Version 7.2 Build 151 09/26/2007 SJ Full Version
38
2275
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
EXERCISE_5_3_4_3
# storage
db|EXERCISE_5_3_4_3.(0).cnf
db|EXERCISE_5_3_4_3.(0).cnf
# case_insensitive
# source_file
EXERCISE_5_3_4_3.bdf
9ea25c261c21dbaf66da588febcaa772
25
# internal_option {
BLOCK_DESIGN_NAMING
OFF
}
# hierarchies {
|
}
# lmf
c:|program files|altera|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
ALU
# storage
db|EXERCISE_5_3_4_3.(1).cnf
db|EXERCISE_5_3_4_3.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
ALU.v
5c6ad128cff5ea8424d0619af940649
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
ALU:inst2
ALU:inst1
ALU:inst
}
# lmf
c:|program files|altera|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# complete