exercise_5_3_4_3.tan.rpt

CLK 为其时钟脉冲 M 控制工作模式 CO 为允许带进位移位输入 S 控制移位模式0-3 D[7..0]是移位数据输入 QB[7..0]是移位数据输出 CN是移位数

Classic Timing Analyzer report for EXERCISE_5_3_4_3
Sat Apr 25 16:12:29 2009
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. tpd
  5. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                  ;
+------------------------------+-------+---------------+-------------+------+-------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From ; To    ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+-------+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 43.028 ns   ; A[3] ; F[20] ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;      ;       ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+------+-------+------------+----------+--------------+


+---------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                      ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                         ; Setting            ; From ; To ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                    ; EP1C12Q240C8       ;      ;    ;             ;
; Timing Models                                                  ; Final              ;      ;    ;             ;
; Default hold multicycle                                        ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                      ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                         ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                 ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                               ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                          ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                        ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                               ; Off                ;      ;    ;             ;
; Enable Clock Latency                                           ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node          ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                          ; 10                 ;      ;    ;             ;
; Number of paths to report                                      ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                   ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                         ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                     ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                   ; Off                ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis ; Off                ;      ;    ;             ;
+----------------------------------------------------------------+--------------------+------+----+-------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; tpd                                                                                                                             ;
+-----------------------------------------+-----------------------------------------------------+-----------------+-------+-------+
; Slack                                   ; Required P2P Time                                   ; Actual P2P Time ; From  ; To    ;
+-----------------------------------------+-----------------------------------------------------+-----------------+-------+-------+
; N/A                                     ; None                                                ; 43.028 ns       ; A[3]  ; F[20] ;
; N/A                                     ; None                                                ; 43.016 ns       ; B[3]  ; F[20] ;
; N/A                                     ; None                                                ; 43.010 ns       ; A[3]  ; F[22] ;
; N/A                                     ; None                                                ; 42.998 ns       ; B[3]  ; F[22] ;
; N/A                                     ; None                                                ; 42.909 ns       ; B[1]  ; F[20] ;
; N/A                                     ; None                                                ; 42.891 ns       ; B[1]  ; F[22] ;
; N/A                                     ; None                                                ; 42.859 ns       ; A[1]  ; F[20] ;
; N/A                                     ; None                                                ; 42.854 ns       ; B[6]  ; F[20] ;
; N/A                                     ; None                                                ; 42.841 ns       ; A[1]  ; F[22] ;
; N/A                                     ; None                                                ; 42.836 ns       ; B[6]  ; F[22] ;
; N/A                                     ; None                                                ; 42.398 ns       ; A[3]  ; F[19] ;
; N/A                                     ; None                                                ; 42.386 ns       ; B[3]  ; F[19] ;
; N/A                                     ; None                                                ; 42.377 ns       ; A[3]  ; F[17] ;
; N/A                                     ; None                                                ; 42.365 ns       ; B[3]  ; F[17] ;
; N/A                                     ; None                                                ; 42.279 ns       ; B[1]  ; F[19] ;
; N/A                                     ; None                                                ; 42.273 ns       ; A[3]  ; F[9]  ;
; N/A                                     ; None                                                ; 42.261 ns       ; B[3]  ; F[9]  ;
; N/A                                     ; None                                                ; 42.258 ns       ; B[1]  ; F[17] ;
; N/A                                     ; None                                                ; 42.229 ns       ; A[1]  ; F[19] ;
; N/A                                     ; None                                                ; 42.224 ns       ; B[6]  ; F[19] ;
; N/A                                     ; None                                                ; 42.208 ns       ; A[1]  ; F[17] ;
; N/A                                     ; None                                                ; 42.204 ns       ; A[3]  ; F[21] ;
; N/A                                     ; None                                                ; 42.203 ns       ; B[6]  ; F[17] ;
; N/A                                     ; None                                                ; 42.192 ns       ; B[3]  ; F[21] ;
; N/A                                     ; None                                                ; 42.154 ns       ; B[1]  ; F[9]  ;
; N/A                                     ; None                                                ; 42.104 ns       ; A[1]  ; F[9]  ;
; N/A                                     ; None                                                ; 42.099 ns       ; B[6]  ; F[9]  ;
; N/A                                     ; None                                                ; 42.085 ns       ; B[1]  ; F[21] ;
; N/A                                     ; None                                                ; 42.035 ns       ; A[1]  ; F[21] ;
; N/A                                     ; None                                                ; 42.030 ns       ; B[6]  ; F[21] ;
; N/A                                     ; None                                                ; 41.844 ns       ; A[3]  ; F[18] ;