uart_top.v

UART程序

module uart_top(clk,rst,send,send_data,send_over,error,recv,
                 recv_data,rxd1,txd1,rxd2,txd2,cs1,cs2);
        input clk,rst,send,rxd1,rxd2,cs1,cs2;
        input[7:0] send_data;
        output send_over,error,recv,txd1,txd2;
        output[7:0] recv_data;
        
        wire rst_parts,ce_parts,bd_out,indicator,send_out;
        wire[7:0] send_parity_source,recv_parity_source,
                  pv_source;
                  
        wire[9:0] send_buf,regs;
        wire sel_pv,parity,overflow,
             new_data,sel_out,rst_dt,sr_out;
             
        wire vcc=1;
         
         wire[4:0] state;
            assign send_parity_source=send_data;
                 
        generator bd_generator(clk,rst_parts,ce_parts,bd_out,indicator);
        
        switcher switcher_bus(send_parity_source,recv_data,
                               sel_pv,pv_source);
                               
        core uart_core(clk,rst,send,send_parity_source,send_over,
                       recv,recv_data,error,sel_pv,parity,
                       rst_parts,ce_parts,overflow,
                        regs,new_data,sel_out,
                         rst_dt,send_buf,state,cs1,cs2);
                         
        counter uart_counter(indicator,rst_parts,ce_parts,overflow);
        
         detector uart_detector(clk,rst_dt,rxd1,new_data);
        
        parity_verifier uart_parity(pv_source,parity);
        
        
        
        shift_register recv_register(bd_out,rst_parts,rxd1,regs,sr_out);
        
        send_register  send_uart_register(bd_out,rst_parts,ce_parts,
                                           send_buf,txd1,txd2,cs1,cs2);
        
        switcher register_clk(bd_out,clk,sel_clk,reg_clk);
        
        
        
endmodule