detector.v

来自「UART程序」· Verilog 代码 · 共 22 行

module detector(clk,rst,rxd,new_data);
    input clk,rst,rxd;
    output new_data;
    reg new_data;
    reg lock;
    
    always @(posedge clk or negedge rst)
    if(!rst)
      begin
          new_data<=0;
          lock<=0;
      end
      else if(rxd==0&&lock==0)
      begin
          new_data<=1;
          lock<=1;
      end
      else
      new_data<=0;
      
  endmodule