send_register.v

来自「UART程序」· Verilog 代码 · 共 40 行

module send_register(clk,rst,ce,din,txd1,txd2,cs1,cs2);
   input clk,rst,ce,cs1,cs2;
   input[9:0] din;
   output txd1,txd2;
   reg txd1,txd2;
 reg[9:0] s_buf;
 

     

   always @(posedge clk or negedge rst)
    if(!rst)
      begin
		s_buf<=din;
       txd1<=1;
       txd2<=1;
      end
    else
      if(ce)
      begin
          if(cs1)
            begin
              txd1<=s_buf[0];
              s_buf<={1'b1,s_buf[9:1]};
              txd2<=1;
            end
          else if(cs2)
             begin
              txd2<=s_buf[0];
              s_buf<={1'b1,s_buf[9:1]};
              txd1<=1;
             end 
             else
               begin
               txd1<=1;
               txd2<=1;
              end  
        end
       
   endmodule