generator.v

来自「UART程序」· Verilog 代码 · 共 35 行

module generator(clk,rst,ce,bd_out,indicator);
    input clk,rst,ce;
    output bd_out,indicator;
    reg indicator;
    reg[15:0] count;
    
    assign bd_out=(count<'d26)?0:1;
    
    always @(posedge clk or negedge rst)
    if(!rst)
      begin
          count<=0;
          indicator<=0;
      end
      else if(ce)
      begin
           if(count=='d52)
           begin
               count<=0;
               indicator<=1;
           end
           else
           begin
               count<=count+1;
               indicator<=0;
           end
       end
       else
         begin
             count<=0;
             indicator<=0;
         end
         
 endmodule