counter.v

来自「UART程序」· Verilog 代码 · 共 34 行

module counter(clk,rst,ce,overflow);
    input clk,rst,ce;
    output overflow;
    reg overflow;
    
    reg[3:0] count;
    
    always @(posedge clk or negedge rst)
    if(!rst)
     begin
         count<=0;
         overflow<=0;
     end
     else if(ce)
     begin
         if(count==4'b1010)
         begin
             count<=0;
             overflow<=1;
         end
         else
         begin
             count<=count+1;
             overflow<=0;
         end
     end
     else
       begin
           count<=0;
         overflow<=0;
     end
 endmodule