core.v

UART程序

module core(clk,rst,send,send_bus,send_over,
            recv,recv_bus,error,sel_pv,parity,
            rst_parts,ce_parts,overflow,
            regs,new_data,sel_out,
            rst_dt,send_buf,state,cs1,cs2);
input clk,rst,send,cs1,cs2;
input[7:0] send_bus;
input parity,overflow,new_data;
output send_over,recv,error,sel_pv,rst_parts,
        ce_parts,rst_dt,sel_out;
input[9:0] regs;
output[7:0] recv_bus;
reg[7:0] recv_bus;
reg send_over,recv,error,sel_pv,rst_parts,
     ce_parts,rst_dt,sel_out;
     
output[4:0] state;
reg[4:0] state;
output[9:0] send_buf;
reg[9:0] send_buf;


parameter idle=5'b00000;

parameter uart_send=5'b00010;
parameter end_send=5'b00100;
parameter uart_recv=5'b01000;
parameter end_recv=5'b10000;

always @(send_bus or parity)
begin
  send_buf[0]<=0;
  send_buf[8:1]<=send_bus;
  send_buf[9]<=parity;
  end
   
always @(posedge clk or negedge rst)
    if(!rst)
      begin
          recv_bus<=0;
        rst_dt<=0;
        rst_parts<=0;
        ce_parts<=0;
        
        sel_pv<=0;
        sel_out<=0;
        send_over<=0;
        recv<=0;
        error<=0;
        state<=idle;
     end
  else
     begin
       case(state)
         idle:begin
               if(new_data==1)
                begin
                 rst_parts<=0;
                 ce_parts<=0;
                
                 sel_out<=0;
                 sel_pv<=1;
                 state<=uart_recv;
               end
            else if(send==1)
               begin
                  rst_parts<=1;
                  ce_parts<=1;
                  sel_out<=0;
                  sel_pv<=0;
                  state<=uart_send;
              end
            else
              begin
              rst_dt<=1;
              state<=idle;
               end
        end
      
           
            uart_send:if(overflow)
                        begin
                        send_over<=1;
                        state<=end_send;
                        end
                    else
                       begin
                         rst_parts<=1;
                         ce_parts<=1;
                         sel_out<=1;
                       end
                       
        end_send:
                   begin
                      ce_parts<=0;
                      rst_parts<=0;
                      rst_dt<=0;
                      send_over<=1;
                    end
                    
        uart_recv:if(overflow)
                     begin
                         recv<=1;
                         state<=end_recv;
                         recv_bus<=regs[7:0];
                      end
                  else
                     begin
                         rst_parts<=1;
                         ce_parts<=1;
                     end
                     
         end_recv:if(regs[1]==parity)
                    begin
                        error<=0;
                        ce_parts<=0;
                        rst_dt<=0;
                        recv<=0;
                        state<=idle;
                    end
                    else
                      begin
                          error<=1;
                          state<=idle;
                      end
             
              endcase
          end
              
      endmodule