receive.vhd

低频数字相位测量仪仿真的软件部分

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity receive is
	port(
		RECCLK: in std_logic;			
		RECDATA: out std_logic;				
		RECEN: in std_logic;		
		ADDRESS:in std_logic_vector(2 downto 0); 
		imbark:in std_logic;
		RECbuff0:in std_logic_vector(15 downto 0);
		RECbuff1:in std_logic_vector(15 downto 0);
		RECbuff2:in std_logic_vector(15 downto 0);
		RECbuff3:in std_logic_vector(15 downto 0);
		RECbuff4:in std_logic_vector(15 downto 0)
		);
end;				
architecture behav of receive is 
signal phase:std_logic_vector(15 downto 0);
signal phase_buf:std_logic_vector(15 downto 0);	
signal datatmp:std_logic;
begin
	process(address,RECbuff0,RECbuff2,RECbuff1,RECbuff4,RECbuff3)
	begin
		case address is
			when "000" =>phase<=RECbuff0;
			when "001" =>phase<=RECbuff1;
			when "010" =>phase<=RECbuff2;
			when "011" =>phase<=RECbuff3; 
			when "100" =>phase<=RECbuff4;
			when others=>phase<=(others=>'0');
		end case;
	end process;
	
	process(RECCLK,RECEN,imbark,phase)
	begin
			if imbark='0' then 	phase_buf <= phase;	
		    elsif(RECCLK'event) and ( RECCLK='1') and (RECEN='1')then
					datatmp<=phase_buf(15);
					phase_buf(15 downto 0)<=phase_buf(14 downto 0)&'0';				
			end if;
	end process;
	RECDATA<=datatmp;		
	end;