countrl.vhd

低频数字相位测量仪仿真的软件部分

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity countrl is
	port(
		CLR: in std_logic;			
		Fa: IN std_logic;				
		Fb: in std_logic;
		Tp:in std_logic;	 
		Tt: buffer std_logic;
		phasen:out std_logic
		);
end;
architecture behav of countrl is  
signal phas: std_logic;
begin
	process(Tp,CLR,Fa)
	begin
		if CLR='1' then Tt<='0';
		elsif Fa'event and Fa='1' then
			Tt<=Tp;
		end if;
		end process; 
		
	process(fa,fb,clr) 
	begin
		if clr='1' then phas<='0';
		else phas<=	fa xor fb	;
		end if;
		end process;
     phasen<=Tt and phas;  
	end behav;