compare4.vhd

来自「这是一个4位比较器的程序」· VHDL 代码 · 共 41 行

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY compare4 IS
PORT(A:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	  B:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
     RST:IN STD_LOGIC;
     CLK:IN STD_LOGIC;
     AGTB:OUT STD_LOGIC; 	
     AEQB:OUT STD_LOGIC; 
     ALTB:OUT STD_LOGIC
     ); 
END compare4;
ARCHITECTURE arch OF compare4 IS
BEGIN
PROCESS(RST,CLK)
BEGIN
IF RST='0' THEN
AGTB<='0';
AEQB<='0';
ALTB<='0';
ELSIF CLK'EVENT AND CLK='1' THEN
  IF A>B THEN
  AGTB<='1';
  AEQB<='0';
  ALTB<='0';
  ELSIF A=B THEN
  AGTB<='0';
  AEQB<='1';
  ALTB<='0'; 
  ELSE
  AGTB<='0';
  AEQB<='0';
  ALTB<='1'; 
  END IF;
END IF;
END PROCESS;
END ARCH;