fenpin_100hz.v

用Verilog HDL编写的秒表设计

module fenpin_100Hz(cin,qout);
	input [18:0] cin;
	output qout;
	
	//reg qout;
	
	assign qout=cin[0]&cin[1]&cin[2]&cin[3]&cin[4]&cin[5]&cin[6]&cin[7]&cin[8]&cin[9]&cin[10];
endmodule